Alternatives and similar repositories for cheshire

Users that are interested in cheshire are comparing it to the libraries listed below

• SpinalHDL / NaxRiscv
  ☆284Updated 2 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆265Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆235Updated 6 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆201Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆252Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆488Updated 3 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆275Updated 2 weeks ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆175Updated last month
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆174Updated 2 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆253Updated this week
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆152Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆211Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 5 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆151Updated this week
• chipsalliance / Cores-VeeR-EH2
  ☆233Updated 2 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 5 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆317Updated 5 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆533Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆324Updated 11 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆194Updated 10 months ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆290Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆173Updated last year
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆180Updated last week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆145Updated 6 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆212Updated 4 years ago
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆97Updated this week
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆223Updated last year
• chipsalliance / VeeR-ISS
  ☆135Updated last year