pulp-platform / cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
☆216Updated this week
Alternatives and similar repositories for cheshire:
Users that are interested in cheshire are comparing it to the libraries listed below
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 2 months ago
- CORE-V Family of RISC-V Cores☆215Updated 11 months ago
- A Fast, Low-Overhead On-chip Network☆155Updated 3 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆236Updated 2 months ago
- VeeR EL2 Core☆257Updated this week
- ☆270Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆203Updated this week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆123Updated this week
- RISC-V System on Chip Template☆155Updated this week
- Verilog Configurable Cache☆170Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆138Updated 2 months ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆280Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆171Updated last year
- Instruction Set Generator initially contributed by Futurewei☆271Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆240Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆450Updated 2 months ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆77Updated this week
- RISC-V 32-bit microcontroller developed in Verilog☆165Updated 2 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆301Updated last month
- RISC-V RV64GC emulator designed for RTL co-simulation☆220Updated last month
- Generic Register Interface (contains various adapters)☆102Updated 3 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆153Updated this week
- ☆166Updated last year
- Opensource DDR3 Controller☆241Updated this week
- RISC-V Formal Verification Framework☆120Updated 3 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆474Updated this week
- Vector processor for RISC-V vector ISA☆112Updated 4 years ago
- ☆220Updated 2 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆300Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆114Updated last week