A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
☆365Aug 28, 2026Updated this week
Alternatives and similar repositories for cheshire
Users that are interested in cheshire are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆127Updated this week
- The multi-core cluster of a PULP system.☆115Aug 4, 2026Updated 3 weeks ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆167Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆235Aug 24, 2026Updated last week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆269Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- GEMM and GEMM-Ops accelerator for PULP systems☆115Aug 5, 2026Updated 3 weeks ago
- A Fast, Low-Overhead On-chip Network☆336Aug 14, 2026Updated 2 weeks ago
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated 3 weeks ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆327Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆147Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆539Aug 19, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,671Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,087Updated this week
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆297Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆65Mar 31, 2025Updated last year
- Common SystemVerilog components☆791Aug 21, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,279Updated this week
- ☆36Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆714Aug 13, 2026Updated 2 weeks ago
- Simple runtime for Pulp platforms☆55Jul 7, 2026Updated last month
- ☆325Jan 23, 2026Updated 7 months ago
- This is the fork of CVA6 intended for PULP development.☆25Updated this week
- RISC-V CPU Core☆445Jun 24, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆96Aug 20, 2026Updated last week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆493May 8, 2026Updated 3 months ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆610Updated this week
- ☆36May 21, 2026Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆113Aug 19, 2026Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆137Jul 11, 2025Updated last year
- A Linux-capable RISC-V multicore for and by the world☆827Jul 13, 2026Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆278Nov 6, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆632Jul 24, 2026Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 7 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆324Updated this week
- DNN Compiler for Heterogeneous SoCs☆75Aug 20, 2026Updated last week
- Input / Output Physical Memory Protection Unit for RISC-V☆15Jul 20, 2023Updated 3 years ago
- SERV - The SErial RISC-V CPU☆1,876Updated this week