Alternatives and similar repositories for cheshire

Users that are interested in cheshire are comparing it to the libraries listed below

• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆302Updated 8 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆277Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆299Updated 2 weeks ago
• SpinalHDL / NaxRiscv
  ☆298Updated last month
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated 3 weeks ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆184Updated last month
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆217Updated this week
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆184Updated last week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 5 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆185Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆295Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆233Updated 11 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆328Updated 10 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆269Updated last month
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆122Updated 2 weeks ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆184Updated 2 weeks ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆231Updated last week
• chipsalliance / Cores-VeeR-EH2
  ☆245Updated 2 years ago
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆306Updated this week
• chipsalliance / VeeR-ISS
  ☆148Updated 2 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated 3 weeks ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆200Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆130Updated last week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆534Updated this week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 3 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆108Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated last year