Alternatives and similar repositories for noc

Users that are interested in noc are comparing it to the libraries listed below

• enjoy-digital / litesata_axiom
  ☆13Updated 4 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 6 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆13Updated 10 months ago
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 4 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• wyvernSemi / usbModel
  USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL
  ☆32Updated last year
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 4 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 6 months ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆14Updated 3 years ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆54Updated 3 weeks ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆18Updated 2 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 3 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 2 months ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆31Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated last month
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• wallento / wb2axi
  Wishbone to ARM AMBA 4 AXI
  ☆16Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆56Updated this week
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆25Updated 10 years ago
• xobs / coriolis
  An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.
  ☆10Updated 7 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 8 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆33Updated 2 months ago
• juliancoy / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆15Updated 3 years ago