Alternatives and similar repositories for noc:

Users that are interested in noc are comparing it to the libraries listed below

• enjoy-digital / litesata_axiom
  ☆12Updated 4 years ago
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 3 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆25Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 4 months ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆11Updated 2 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆12Updated 4 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 3 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• chipsalliance / tools-cocotb-verilator-build
  ☆13Updated 5 years ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆27Updated last year
• chipsalliance / f4pga-xc7-bram-patch
  Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
  ☆18Updated 3 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆22Updated last week
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated last month
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 2 months ago
• pulp-platform / apb
  APB Logic
  ☆14Updated 2 months ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• pulp-platform / hier-icache
  ☆11Updated 11 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆30Updated 2 weeks ago
• rohitk-singh / usb-device
  USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
  ☆12Updated 7 years ago
• ultraembedded / core_ram_tester
  AXI-4 RAM Tester Component
  ☆17Updated 4 years ago
• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆13Updated 9 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 7 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago