ueqri / vis4meshLinks
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
☆16Updated last year
Alternatives and similar repositories for vis4mesh
Users that are interested in vis4mesh are comparing it to the libraries listed below
Sorting:
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- RISC-V SST CPU Component☆24Updated 2 months ago
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆43Updated 5 months ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆44Updated 8 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆34Updated last year
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 10 months ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- ☆39Updated 8 months ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆23Updated last year
- ☆13Updated 6 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆30Updated 2 weeks ago
- ☆106Updated last year
- RISC-V Matrix Specification☆23Updated 11 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆24Updated this week
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Updated 4 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 2 months ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆20Updated 6 years ago
- A Heterogeneous GPU Platform for Chipyard SoC☆39Updated this week
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆22Updated last year
- Tutorial Material from the SST Team☆25Updated 3 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- corundum work on vu13p☆23Updated 2 years ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- Championship Value Prediction (CVP) simulator.☆17Updated 4 years ago