ueqri / vis4meshLinks
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
☆11Updated last year
Alternatives and similar repositories for vis4mesh
Users that are interested in vis4mesh are comparing it to the libraries listed below
Sorting:
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…☆21Updated 11 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆19Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆36Updated 5 months ago
- Tutorial Material from the SST Team☆19Updated this week
- ☆19Updated 5 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆20Updated 4 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- ☆21Updated last year
- ☆30Updated 2 months ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- A parallel and distributed simulator for thousand-core chips☆24Updated 7 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆26Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆31Updated 2 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆26Updated 4 months ago
- RISC-V SST CPU Component☆24Updated this week
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11Updated 3 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆22Updated last year
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆21Updated 3 weeks ago
- Championship Value Prediction (CVP) simulator.☆17Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- This simulator models multi core systems, intended primarily for studies on main memory management techniques. It models a trace-based ou…☆10Updated 9 years ago