Alternatives and similar repositories for core-v-cores

Users that are interested in core-v-cores are comparing it to the libraries listed below

• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆300Updated last week
• SpinalHDL / NaxRiscv
  ☆300Updated 2 weeks ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated 2 weeks ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆190Updated 2 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆283Updated last week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆304Updated 2 weeks ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆187Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆246Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆248Updated 2 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆394Updated 5 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆448Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆544Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆364Updated 9 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆235Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆296Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆621Updated last month
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆275Updated 2 months ago
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆157Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 4 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆190Updated 3 weeks ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆126Updated last week
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆224Updated last week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 5 years ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆223Updated 9 months ago