Alternatives and similar repositories for core-v-cores

Users that are interested in core-v-cores are comparing it to the libraries listed below

• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆181Updated 2 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆239Updated 8 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆217Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆260Updated 2 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆271Updated this week
• SpinalHDL / NaxRiscv
  ☆291Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆288Updated 2 weeks ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆174Updated 3 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆239Updated 2 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆348Updated 2 weeks ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆397Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆510Updated 5 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆333Updated 4 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 8 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆289Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆109Updated last month
• chipsalliance / VeeR-ISS
  ☆139Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆634Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 7 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆123Updated last month
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated 3 weeks ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆104Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆563Updated last week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆290Updated last week
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆300Updated this week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆201Updated last week
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆394Updated 6 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago