openhwgroup / core-v-coresLinks
CORE-V Family of RISC-V Cores
☆299Updated 7 months ago
Alternatives and similar repositories for core-v-cores
Users that are interested in core-v-cores are comparing it to the libraries listed below
Sorting:
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated 2 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆286Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆324Updated 9 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆245Updated 10 months ago
- ☆296Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 4 months ago
- VeeR EL2 Core☆297Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆273Updated last week
- ☆244Updated 2 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆415Updated 2 weeks ago
- RISC-V CPU Core☆387Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- RISC-V microcontroller IP core developed in Verilog☆183Updated 5 months ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated last year
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆349Updated 7 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated last week
- Arduino compatible Risc-V Based SOC☆156Updated last year
- Common SystemVerilog components☆660Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆266Updated last week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆179Updated last week
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆306Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆599Updated last week
- ☆145Updated last year
- RISC-V RV64GC emulator designed for RTL co-simulation☆230Updated 10 months ago
- RISC-V System on Chip Template☆159Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆513Updated 10 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- Generic Register Interface (contains various adapters)☆130Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 11 months ago