Alternatives and similar repositories for core-v-cores:

Users that are interested in core-v-cores are comparing it to the libraries listed below

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• SpinalHDL / NaxRiscv
  ☆279Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆206Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆308Updated 3 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆266Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆232Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆460Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆506Updated this week
• rafaelcalcada / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆168Updated 3 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆273Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆587Updated 2 weeks ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆279Updated this week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆326Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 4 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆230Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆178Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆153Updated 11 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆247Updated 2 weeks ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆132Updated 5 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆144Updated 8 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆111Updated 5 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆135Updated 3 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆143Updated 4 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆667Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆559Updated last week