CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
☆525Apr 27, 2026Updated last week
Alternatives and similar repositories for cvw
Users that are interested in cvw are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The purpose of the repo is to support CORE-V Wally architectural verification☆18Nov 11, 2025Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆131Jul 11, 2025Updated 9 months ago
- A Linux-capable RISC-V multicore for and by the world☆798Apr 24, 2026Updated last week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆220Apr 24, 2026Updated last week
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆594Apr 20, 2026Updated 2 weeks ago
- 32-bit Superscalar RISC-V CPU☆1,239Sep 18, 2021Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,913Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆979Nov 15, 2024Updated last year
- ☆314Jan 23, 2026Updated 3 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆149Updated this week
- RISC-V XV6/Linux SoC, marchID: 0x2b☆1,086Mar 3, 2026Updated 2 months ago
- CORE-V Family of RISC-V Cores☆351Mar 31, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,223Apr 17, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆269Nov 6, 2024Updated last year
- Advanced Architecture Labs with CVA6☆82Jan 16, 2024Updated 2 years ago
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆262Apr 24, 2026Updated last week
- Common SystemVerilog components☆738Apr 27, 2026Updated last week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆331Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,170Feb 21, 2026Updated 2 months ago
- 64-bit multicore Linux-capable RISC-V processor☆111Apr 28, 2025Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 10 months ago
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆692Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆85Apr 1, 2026Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆89Nov 26, 2025Updated 5 months ago
- SERV - The SErial RISC-V CPU☆1,791Feb 19, 2026Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆114Apr 22, 2026Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆515Apr 24, 2026Updated last week
- VeeR EL2 Core☆335Updated this week
- ☆1,996Updated this week
- Learning FPGA, yosys, nextpnr, and RISC-V☆3,486Nov 18, 2025Updated 5 months ago
- VRoom! RISC-V CPU☆520Sep 2, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,864Apr 14, 2026Updated 2 weeks ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- RISC-V Zve32x Vector Coprocessor☆216Jan 22, 2026Updated 3 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆318Apr 15, 2026Updated 2 weeks ago
- ☆102Mar 5, 2026Updated last month
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Apr 26, 2026Updated last week
- Linux capable RISC-V SoC designed to be readable and useful.☆161Dec 19, 2025Updated 4 months ago