Alternatives and similar repositories for cvw

Users that are interested in cvw are comparing it to the libraries listed below

• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆314Updated 10 months ago
• SpinalHDL / NaxRiscv
  ☆301Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated 2 weeks ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆250Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆554Updated 2 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆198Updated 4 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆312Updated 2 weeks ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated last month
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆336Updated last year
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆370Updated 10 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆753Updated last month
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆692Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆631Updated 2 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆401Updated 6 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆629Updated 2 weeks ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated 3 weeks ago
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆313Updated 3 weeks ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆688Updated last month
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• riscv-non-isa / riscv-arch-test
  ☆625Updated this week
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆307Updated 2 weeks ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 6 years ago
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆286Updated 11 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆368Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆130Updated 3 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆417Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆473Updated 2 months ago