Alternatives and similar repositories for cvw

Users that are interested in cvw are comparing it to the libraries listed below

• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆318Updated 11 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆253Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆290Updated last month
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆190Updated last week
• SpinalHDL / NaxRiscv
  ☆306Updated 2 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆316Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆195Updated last month
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆758Updated last week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆200Updated 4 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆374Updated 11 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆561Updated 3 months ago
• riscv-non-isa / riscv-arch-test
  ☆638Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆404Updated 7 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆648Updated 2 weeks ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆315Updated 3 weeks ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆422Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆700Updated last month
• suryakantamangaraj / AwesomeRISC-VResources
  It contains a curated list of awesome RISC-V Resources.
  ☆291Updated last year
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆436Updated 3 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆153Updated 6 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆761Updated 4 months ago
• chipfoundry / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆329Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆638Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆304Updated 2 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆238Updated last year
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆283Updated last year
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆225Updated 11 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆375Updated 2 years ago