openhwgroup / cvwLinks
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
☆428Updated last week
Alternatives and similar repositories for cvw
Users that are interested in cvw are comparing it to the libraries listed below
Sorting:
- CORE-V Family of RISC-V Cores☆302Updated 8 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆274Updated last week
- RISC-V microcontroller IP core developed in Verilog☆183Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆328Updated 10 months ago
- A simple RISC V core for teaching☆197Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆244Updated 11 months ago
- ☆297Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 5 months ago
- A Linux-capable RISC-V multicore for and by the world☆741Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆356Updated 7 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆291Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆186Updated 3 weeks ago
- SystemVerilog to Verilog conversion☆670Updated 4 months ago
- RISC-V CPU Core☆389Updated 4 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆602Updated last week
- Common SystemVerilog components☆665Updated 3 weeks ago
- VeeR EL2 Core☆299Updated 2 weeks ago
- FOSS Flow For FPGA☆409Updated 9 months ago
- ☆352Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆612Updated 2 weeks ago
- A 256-RISC-V-core system with low-latency access into shared L1 memory.☆306Updated this week
- Ariane is a 6-stage RISC-V CPU☆149Updated 5 years ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆315Updated 7 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆233Updated 11 months ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated 2 years ago
- Small footprint and configurable DRAM core☆444Updated last week
- https://caravel-user-project.readthedocs.io☆221Updated 7 months ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆447Updated last year
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated this week