RISC-V Verification Interface
☆152Mar 27, 2026Updated last month
Alternatives and similar repositories for RVVI
Users that are interested in RVVI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog Functional Coverage for RISC-V ISA☆36Dec 11, 2025Updated 5 months ago
- ☆201Dec 14, 2023Updated 2 years ago
- Functional verification project for the CORE-V family of RISC-V cores.☆683Apr 16, 2026Updated last month
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- Random instruction generator for RISC-V processor verification☆1,303Apr 3, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 3 months ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated 4 months ago
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆707Updated this week
- ☆13Aug 22, 2022Updated 3 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- RISC-V Virtual Prototype☆188Dec 13, 2024Updated last year
- RISC-V Torture Test☆216Jul 11, 2024Updated last year
- The purpose of the repo is to support CORE-V Wally architectural verification☆18Nov 11, 2025Updated 6 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Instruction Set Generator initially contributed by Futurewei☆310Oct 17, 2023Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆342Dec 11, 2024Updated last year
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆135Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆241Nov 20, 2024Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- CMake based hardware build system☆40Updated this week
- RISC-V Formal Verification Framework☆631Apr 6, 2022Updated 4 years ago
- An instruction set simulator based on DBT-RISE implementing the RISC-V ISA☆37May 15, 2026Updated last week
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆204Updated this week
- SystemC Configuration, Control and Inspection (CCI)☆19Nov 25, 2025Updated 6 months ago
- UVM interactive debug library☆36Feb 28, 2026Updated 2 months ago
- A modeling library with virtual components for SystemC and TLM simulators☆190May 16, 2026Updated last week
- C library for the emulation of reduced-precision floating point types☆56Apr 2, 2023Updated 3 years ago
- Sail RISC-V model☆705May 18, 2026Updated last week
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆65May 18, 2026Updated last week
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 2 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆23Apr 25, 2025Updated last year
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆25Jan 6, 2026Updated 4 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 4 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,883May 7, 2026Updated 2 weeks ago
- PLIC Specification☆152Apr 8, 2026Updated last month
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- ☆265Dec 22, 2022Updated 3 years ago