riscv-verification / RVVI
RISC-V Verification Interface
☆76Updated 2 months ago
Related projects ⓘ
Alternatives and complementary repositories for RVVI
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- A Fast, Low-Overhead On-chip Network☆140Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- ☆75Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- RISC-V System on Chip Template☆153Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆114Updated 2 months ago
- Ariane is a 6-stage RISC-V CPU☆124Updated 4 years ago
- Generic Register Interface (contains various adapters)☆100Updated last month
- Verilog Configurable Cache☆167Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- Network on Chip Implementation written in SytemVerilog☆158Updated 2 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆53Updated 4 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆59Updated last month
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆148Updated this week
- An Open-Source Design and Verification Environment for RISC-V☆76Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆169Updated 10 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- ☆161Updated 11 months ago
- SystemVerilog synthesis tool☆169Updated this week
- CVA6 SDK containing RISC-V tools and Buildroot☆62Updated 5 months ago
- Control and status register code generator toolchain☆105Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆108Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- ☆42Updated 8 years ago
- Vector processor for RISC-V vector ISA☆110Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆202Updated last week
- A dynamic verification library for Chisel.☆142Updated 2 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago