riscv-verification / RVVI
RISC-V Verification Interface
☆84Updated last week
Alternatives and similar repositories for RVVI:
Users that are interested in RVVI are comparing it to the libraries listed below
- ☆87Updated last year
- Generic Register Interface (contains various adapters)☆109Updated 5 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆117Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆123Updated this week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- A Fast, Low-Overhead On-chip Network☆175Updated this week
- ☆45Updated 8 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 3 weeks ago
- ☆77Updated last month
- Basic RISC-V Test SoC☆112Updated 5 years ago
- Network on Chip Implementation written in SytemVerilog☆168Updated 2 years ago
- Control and status register code generator toolchain☆112Updated 2 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆71Updated 11 months ago
- ☆73Updated 6 months ago
- RISC-V System on Chip Template☆156Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 2 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆142Updated 8 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆162Updated 3 months ago
- SystemVerilog synthesis tool☆178Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 6 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆61Updated 3 months ago
- ☆168Updated last year
- Ariane is a 6-stage RISC-V CPU☆131Updated 5 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆209Updated this week
- Verilog Configurable Cache☆171Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated last month
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆198Updated 4 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆55Updated this week