riscv-verification / RVVILinks
RISC-V Verification Interface
☆103Updated this week
Alternatives and similar repositories for RVVI
Users that are interested in RVVI are comparing it to the libraries listed below
Sorting:
- ☆97Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- RISC-V System on Chip Template☆159Updated last month
- ☆95Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆84Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆126Updated last week
- ☆189Updated last year
- Generic Register Interface (contains various adapters)☆130Updated last month
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆183Updated last week
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Platform Level Interrupt Controller☆43Updated last year
- CVA6 SDK containing RISC-V tools and Buildroot☆74Updated 3 months ago
- The multi-core cluster of a PULP system.☆108Updated 2 weeks ago
- RISC-V Virtual Prototype☆177Updated 9 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- A dynamic verification library for Chisel.☆155Updated 10 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 6 months ago
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆74Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆140Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆117Updated this week
- SystemVerilog synthesis tool☆211Updated 6 months ago