riscv-verification / RVVILinks
RISC-V Verification Interface
☆141Updated 2 weeks ago
Alternatives and similar repositories for RVVI
Users that are interested in RVVI are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 7 months ago
- Generic Register Interface (contains various adapters)☆135Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated last week
- RISC-V System on Chip Template☆160Updated 5 months ago
- ☆114Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last week
- pulp_soc is the core building component of PULP based SoCs☆82Updated 11 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- ☆101Updated 5 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆196Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated last week
- Vector processor for RISC-V vector ISA☆136Updated 5 years ago
- Network on Chip Implementation written in SytemVerilog☆198Updated 3 years ago
- An Open-Source Design and Verification Environment for RISC-V☆87Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated last week
- ☆193Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆267Updated 2 weeks ago
- Verilog Configurable Cache☆192Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆111Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- Platform Level Interrupt Controller☆44Updated last year
- Ariane is a 6-stage RISC-V CPU☆153Updated 6 years ago
- SystemRDL 2.0 language compiler front-end☆271Updated 3 weeks ago
- Verilog/SystemVerilog Guide☆80Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- Simple single-port AXI memory interface☆49Updated last year
- SystemVerilog synthesis tool☆227Updated 11 months ago
- Basic RISC-V Test SoC☆173Updated 6 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 3 months ago