Alternatives and similar repositories for pulp

Users that are interested in pulp are comparing it to the libraries listed below

• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 6 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆673Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆542Updated 3 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆614Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆616Updated this week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆468Updated 3 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆303Updated this week
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,138Updated 5 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,405Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆393Updated 4 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆463Updated last week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆673Updated 2 weeks ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆280Updated last week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆603Updated 7 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆906Updated 2 years ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆747Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆300Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆355Updated 2 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆693Updated 2 years ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆742Updated last month
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,196Updated last month
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆959Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆247Updated 2 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆391Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆304Updated 9 months ago
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆616Updated 3 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆481Updated last week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆939Updated last year