openhwgroup / core-v-verifLinks
Functional verification project for the CORE-V family of RISC-V cores.
☆602Updated last week
Alternatives and similar repositories for core-v-verif
Users that are interested in core-v-verif are comparing it to the libraries listed below
Sorting:
- Common SystemVerilog components☆665Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆444Updated 5 months ago
- VeeR EL2 Core☆299Updated 2 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆295Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆328Updated 10 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,385Updated last week
- BaseJump STL: A Standard Template Library for SystemVerilog☆612Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,122Updated 4 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆515Updated 10 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆274Updated last week
- RISC-V CPU Core☆389Updated 3 months ago
- A Linux-capable RISC-V multicore for and by the world☆741Updated 2 weeks ago
- VeeR EH1 core☆900Updated 2 years ago
- ☆598Updated last week
- Random instruction generator for RISC-V processor verification☆1,177Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆465Updated 2 months ago
- lowRISC Style Guides☆460Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆1,106Updated 4 years ago
- The OpenPiton Platform☆732Updated 3 weeks ago
- SystemVerilog to Verilog conversion☆670Updated 4 months ago
- AMBA AXI VIP☆426Updated last year
- Bus bridges and other odds and ends☆593Updated 6 months ago
- ☆245Updated 2 years ago
- CORE-V Family of RISC-V Cores☆302Updated 8 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆525Updated 4 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆936Updated 11 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆275Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆387Updated last month
- The UVM written in Python☆464Updated last week