Alternatives and similar repositories for core-v-verif

Users that are interested in core-v-verif are comparing it to the libraries listed below

• pulp-platform / common_cells
  Common SystemVerilog components
  ☆649Updated this week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆525Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆292Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆294Updated last week
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆598Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆438Updated 3 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆509Updated 8 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆323Updated 8 months ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,109Updated 2 months ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆266Updated 4 months ago
• riscv-non-isa / riscv-arch-test
  ☆583Updated this week
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆889Updated 2 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,353Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆448Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆721Updated this week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆369Updated last month
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆453Updated 3 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆287Updated 6 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,086Updated 3 years ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆659Updated 2 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,153Updated 2 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆273Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆242Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆582Updated 4 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆727Updated last month
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆275Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆338Updated this week
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆926Updated 9 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆936Updated last month