openhwgroup / core-v-verifView external linksLinks
Functional verification project for the CORE-V family of RISC-V cores.
☆656Updated this week
Alternatives and similar repositories for core-v-verif
Users that are interested in core-v-verif are comparing it to the libraries listed below
Sorting:
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Jan 11, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,183May 26, 2025Updated 8 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆258Nov 6, 2024Updated last year
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,252Oct 1, 2025Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆155Oct 31, 2024Updated last year
- CORE-V Family of RISC-V Cores☆327Feb 13, 2025Updated last year
- Common SystemVerilog components☆706Feb 6, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,764Feb 7, 2026Updated last week
- AMBA AXI VIP☆447Jun 28, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,797Updated this week
- RISC-V Verification Interface☆141Jan 28, 2026Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆569Oct 21, 2025Updated 3 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆294Feb 4, 2026Updated last week
- Generic Register Interface (contains various adapters)☆135Nov 20, 2025Updated 2 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,492Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆196Dec 11, 2025Updated 2 months ago
- The multi-core cluster of a PULP system.☆111Feb 2, 2026Updated last week
- VeeR EH1 core☆923May 29, 2023Updated 2 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Mar 10, 2025Updated 11 months ago
- ☆650Updated this week
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Feb 5, 2026Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆335Dec 11, 2024Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆317Updated this week
- VeeR EL2 Core☆317Dec 29, 2025Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆87Apr 21, 2021Updated 4 years ago
- OpenTitan: Open source silicon root of trust☆3,132Updated this week
- Working Draft of the RISC-V Debug Specification Standard☆504Feb 5, 2026Updated last week
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- RISC-V CPU Core☆405Jun 24, 2025Updated 7 months ago
- A Linux-capable RISC-V multicore for and by the world☆761Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Feb 5, 2026Updated last week
- 32-bit Superscalar RISC-V CPU☆1,176Sep 18, 2021Updated 4 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆276Jan 10, 2026Updated last month
- RISC-V Torture Test☆213Jul 11, 2024Updated last year
- Awesome ASIC design verification☆341Feb 9, 2022Updated 4 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆238Nov 20, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,138Updated this week