Functional verification project for the CORE-V family of RISC-V cores.
☆659Mar 4, 2026Updated this week
Alternatives and similar repositories for core-v-verif
Users that are interested in core-v-verif are comparing it to the libraries listed below
Sorting:
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆225Jan 11, 2026Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,190May 26, 2025Updated 9 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆259Nov 6, 2024Updated last year
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- Random instruction generator for RISC-V processor verification☆1,257Oct 1, 2025Updated 5 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆156Oct 31, 2024Updated last year
- CORE-V Family of RISC-V Cores☆332Feb 13, 2025Updated last year
- Common SystemVerilog components☆713Feb 26, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,774Feb 17, 2026Updated 2 weeks ago
- AMBA AXI VIP☆448Jun 28, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,828Feb 25, 2026Updated last week
- RISC-V Verification Interface☆142Jan 28, 2026Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆571Oct 21, 2025Updated 4 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆297Feb 4, 2026Updated last month
- Generic Register Interface (contains various adapters)☆136Feb 24, 2026Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Feb 25, 2026Updated last week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆195Feb 12, 2026Updated 3 weeks ago
- The multi-core cluster of a PULP system.☆111Updated this week
- pulp_soc is the core building component of PULP based SoCs☆82Mar 10, 2025Updated 11 months ago
- VeeR EH1 core☆929May 29, 2023Updated 2 years ago
- ☆652Updated this week
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Dec 11, 2024Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆320Feb 24, 2026Updated last week
- VeeR EL2 Core☆318Feb 23, 2026Updated last week
- An Open-Source Design and Verification Environment for RISC-V☆87Apr 21, 2021Updated 4 years ago
- OpenTitan: Open source silicon root of trust☆3,175Updated this week
- Working Draft of the RISC-V Debug Specification Standard☆505Updated this week
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- 32-bit Superscalar RISC-V CPU☆1,183Sep 18, 2021Updated 4 years ago
- RISC-V CPU Core☆411Jun 24, 2025Updated 8 months ago
- A Linux-capable RISC-V multicore for and by the world☆771Feb 9, 2026Updated 3 weeks ago
- Tile based architecture designed for computing efficiency, scalability and generality☆279Feb 20, 2026Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆197Updated this week
- RISC-V Torture Test☆213Jul 11, 2024Updated last year
- Awesome ASIC design verification☆343Feb 9, 2022Updated 4 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,160Updated this week