Functional verification project for the CORE-V family of RISC-V cores.
☆711Aug 13, 2026Updated this week
Alternatives and similar repositories for core-v-verif
Users that are interested in core-v-verif are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 7 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,274May 29, 2026Updated 2 months ago
- Random instruction generator for RISC-V processor verification☆1,344Apr 3, 2026Updated 4 months ago
- Instruction Set Generator initially contributed by Futurewei☆312Oct 17, 2023Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆277Nov 6, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- AMBA AXI VIP☆472Jun 28, 2024Updated 2 years ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,015Aug 11, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,068Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆162Oct 31, 2024Updated last year
- CORE-V Family of RISC-V Cores☆367Mar 31, 2026Updated 4 months ago
- RISC-V Verification Interface☆158Jun 11, 2026Updated 2 months ago
- RISC-V Formal Verification Framework☆633Apr 6, 2022Updated 4 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆632Jul 24, 2026Updated 3 weeks ago
- Common SystemVerilog components☆783Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- An Open-Source Design and Verification Environment for RISC-V☆90Apr 21, 2021Updated 5 years ago
- The RISC-V Architectural Certification Tests (ACTs) are a set of assembly language tests designed to certify that a design faithfully imp…☆770Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆211Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,659Aug 5, 2026Updated last week
- VeeR EH1 core☆961Jul 16, 2026Updated last month
- Generic Register Interface (contains various adapters)☆141Aug 6, 2026Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆323Updated this week
- pulp_soc is the core building component of PULP based SoCs☆85Jul 17, 2026Updated last month
- The multi-core cluster of a PULP system.☆115Aug 4, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆361Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆37Aug 7, 2026Updated last week
- OpenTitan: Open source silicon root of trust☆3,598Updated this week
- Awesome ASIC design verification☆364Feb 9, 2022Updated 4 years ago
- RISC-V Torture Test☆221Jul 11, 2024Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆341Dec 11, 2024Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆36Dec 11, 2025Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆96Jul 22, 2026Updated 3 weeks ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VeeR EL2 Core☆344Updated this week
- Spike, a RISC-V ISA Simulator☆3,200Updated this week
- A Framework for Design and Verification of Image Processing Applications using UVM☆121Nov 27, 2017Updated 8 years ago
- RISC-V Debug Specification Standard☆526Jul 21, 2026Updated 3 weeks ago
- ☆158Oct 6, 2023Updated 2 years ago
- ☆203Dec 14, 2023Updated 2 years ago
- RISC-V CPU Core☆443Jun 24, 2025Updated last year