IObundle / iob-soc
RISC-V System on Chip Template
☆156Updated this week
Alternatives and similar repositories for iob-soc:
Users that are interested in iob-soc are comparing it to the libraries listed below
- Verilog Configurable Cache☆174Updated 3 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago
- RISC-V Verification Interface☆85Updated last month
- An Open-Source Design and Verification Environment for RISC-V☆79Updated 3 years ago
- Generic Register Interface (contains various adapters)☆111Updated 5 months ago
- Ariane is a 6-stage RISC-V CPU☆132Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆139Updated 2 weeks ago
- The multi-core cluster of a PULP system.☆85Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 weeks ago
- ☆88Updated last year
- RISC-V microcontroller IP core developed in Verilog☆169Updated this week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆182Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 4 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- ☆169Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated this week
- A dynamic verification library for Chisel.☆147Updated 4 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆149Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 4 months ago
- Basic RISC-V Test SoC☆118Updated 5 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- Vector processor for RISC-V vector ISA☆116Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago