Alternatives and similar repositories for iob-soc

Users that are interested in iob-soc are comparing it to the libraries listed below

• IObundle / iob-cache
  Verilog Configurable Cache
  ☆190Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆136Updated last month
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆192Updated 3 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆134Updated last month
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆252Updated last year
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆166Updated 6 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆313Updated last week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆132Updated 3 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 10 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆86Updated 4 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆192Updated 2 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆153Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆79Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆80Updated last week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆145Updated last week
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆99Updated 4 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated 2 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆259Updated 3 weeks ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆134Updated 5 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆311Updated 2 weeks ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆185Updated last year
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆289Updated 3 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆223Updated 10 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week