RISC-V System on Chip Template
☆161Aug 18, 2025Updated 7 months ago
Alternatives and similar repositories for iob-soc
Users that are interested in iob-soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Coarse Grained Reconfigurable Array☆20Feb 18, 2026Updated last month
- Running Linux on IOb-SoC-OpenCryptoHW☆15Aug 15, 2024Updated last year
- Verilog Configurable Cache☆193Mar 9, 2026Updated 2 weeks ago
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆13Feb 23, 2025Updated last year
- a Python framework for managing embedded HW/SW projects☆21Feb 26, 2026Updated 3 weeks ago
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 3 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆156Oct 31, 2024Updated last year
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- CORE-V Family of RISC-V Cores☆340Feb 13, 2025Updated last year
- Synthesizable and Parameterized Cache Controller in Verilog☆45Jun 13, 2023Updated 2 years ago
- Hardware random number generator for FPGAs☆10May 7, 2015Updated 10 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆323Updated this week
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- ☆33Nov 25, 2022Updated 3 years ago
- Basic RISC-V Test SoC☆181Apr 7, 2019Updated 6 years ago
- A Linux-capable RISC-V multicore for and by the world☆784Updated this week
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆193Updated this week
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated 3 weeks ago
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆970Nov 15, 2024Updated last year
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Apr 27, 2024Updated last year
- 32-bit Superscalar RISC-V CPU☆1,197Sep 18, 2021Updated 4 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆228Aug 25, 2020Updated 5 years ago
- Two Level Cache Controller implementation in Verilog HDL☆60Jul 9, 2020Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆338Dec 11, 2024Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆577Mar 11, 2026Updated last week
- Simple 3-stage pipeline RISC-V processor☆146Feb 24, 2026Updated last month
- RISC-V CPU Core☆417Jun 24, 2025Updated 8 months ago
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆315Feb 11, 2026Updated last month
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- A modular and multifunctional embedded platform designed for mobile robotics applications.☆16Jun 3, 2024Updated last year
- Common SystemVerilog components☆728Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆281Feb 20, 2026Updated last month
- Verilog library for ASIC and FPGA designers☆1,397May 8, 2024Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,157Feb 21, 2026Updated last month
- AMBA bus generator including AXI, AHB, and APB☆121Jul 29, 2021Updated 4 years ago
- Verilog AXI components for FPGA implementation☆1,987Feb 27, 2025Updated last year