Alternatives and similar repositories for cv32e41p

Users that are interested in cv32e41p are comparing it to the libraries listed below

• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 10 months ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆50Updated 2 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆79Updated last year
• riscv-software-src / riscv-ctg
  ☆41Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆153Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆75Updated last month
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆28Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆34Updated 9 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆72Updated last year
• lowRISC / lowrisc-toolchains
  UNSUPPORTED INTERNAL toolchain builds
  ☆47Updated last month
• verilator / example-systemverilog
  ☆40Updated last year
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• riscv / riscv-test-env
  ☆51Updated this week
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆134Updated last month
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 2 months ago
• pulp-platform / axi_llc
  ☆33Updated last month
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆19Updated last year
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆33Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated last week