4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
☆26Aug 16, 2023Updated 2 years ago
Alternatives and similar repositories for cv32e41p
Users that are interested in cv32e41p are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆267Nov 6, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆194Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆60Apr 3, 2026Updated 2 weeks ago
- VeeR EL2 Core☆332Mar 12, 2026Updated last month
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆102Jun 24, 2025Updated 9 months ago
- ☆12Feb 15, 2024Updated 2 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Updated this week
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆22Nov 21, 2020Updated 5 years ago
- ☆42Nov 4, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆263Dec 22, 2022Updated 3 years ago
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated last month
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 6 months ago
- VeeR EH1 core☆935May 29, 2023Updated 2 years ago
- HARV - HArdened Risc-V☆16Mar 10, 2022Updated 4 years ago
- Parametric GPIO Peripheral☆12Jan 30, 2025Updated last year
- Build scripts of ci.rvperf.org☆12Apr 10, 2026Updated last week
- JTAG Test Access Port (TAP)☆39Jul 17, 2014Updated 11 years ago
- ☆36Nov 4, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- A recruitment website for OpenCAS base on Meteor.☆10May 21, 2015Updated 10 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Nov 26, 2024Updated last year
- Documentation and status of UEFI on RISC-V☆64Aug 25, 2021Updated 4 years ago
- Generic Register Interface (contains various adapters)☆138Feb 24, 2026Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆184Apr 4, 2026Updated 2 weeks ago
- ☆38Mar 7, 2026Updated last month
- C/C++ Dynamic Memory Analyzer (CMA)☆18Jul 29, 2014Updated 11 years ago
- The OpenPiton Platform☆31May 22, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A collection of mesh routing protocols.☆28Jul 24, 2025Updated 8 months ago
- ☆155Oct 6, 2023Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Nov 1, 2020Updated 5 years ago
- ☆15Nov 8, 2019Updated 6 years ago
- A formalization of the RVWMO (RISC-V) memory model☆37Jun 23, 2022Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,213May 26, 2025Updated 10 months ago