4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
☆27Aug 16, 2023Updated 2 years ago
Alternatives and similar repositories for cv32e41p
Users that are interested in cv32e41p are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆161Oct 31, 2024Updated last year
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆275Nov 6, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 3 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 3 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- RISC-V microcontroller for embedded, FPGA and ASIC applications☆200Jul 19, 2026Updated last week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Feb 6, 2024Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- VeeR EL2 Core☆342Updated this week
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 3 months ago
- ☆12Feb 15, 2024Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆105Jun 24, 2025Updated last year
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆62Jun 18, 2026Updated last month
- ☆43Nov 4, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆25Nov 21, 2020Updated 5 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- VeeR EH2 core☆274Jul 20, 2026Updated last week
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated 5 months ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 9 months ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- VeeR EH1 core☆957Jul 16, 2026Updated last week
- HARV - HArdened Risc-V☆18Mar 10, 2022Updated 4 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆67Jul 17, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 5 years ago
- JTAG Test Access Port (TAP)☆41Jul 17, 2014Updated 12 years ago
- Parametric GPIO Peripheral☆13Jan 30, 2025Updated last year
- CORE-V Family of RISC-V Cores☆364Mar 31, 2026Updated 3 months ago
- Build scripts of ci.rvperf.org☆12Apr 10, 2026Updated 3 months ago
- ☆36Nov 4, 2024Updated last year
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆20Nov 26, 2024Updated last year
- Generic Register Interface (contains various adapters)☆141Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Documentation and status of UEFI on RISC-V☆64Aug 25, 2021Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆191Apr 4, 2026Updated 3 months ago
- The OpenPiton Platform☆31May 22, 2023Updated 3 years ago
- ☆39Updated this week
- ☆157Oct 6, 2023Updated 2 years ago
- A collection of mesh routing protocols.☆29Jul 24, 2025Updated last year
- This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.☆17Updated this week