4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
☆27Aug 16, 2023Updated 2 years ago
Alternatives and similar repositories for cv32e41p
Users that are interested in cv32e41p are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆272Nov 6, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 27, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆200May 26, 2026Updated 3 weeks ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- RISC-V Configuration Validator☆82Apr 16, 2026Updated 2 months ago
- VeeR EL2 Core☆338Jun 5, 2026Updated last week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆62Apr 3, 2026Updated 2 months ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- ☆12Feb 15, 2024Updated 2 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆24Nov 21, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆42Nov 4, 2024Updated last year
- ☆265Dec 22, 2022Updated 3 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated 3 months ago
- VeeR EH1 core☆949May 29, 2023Updated 3 years ago
- HARV - HArdened Risc-V☆16Mar 10, 2022Updated 4 years ago
- Parametric GPIO Peripheral☆13Jan 30, 2025Updated last year
- Build scripts of ci.rvperf.org☆12Apr 10, 2026Updated 2 months ago
- JTAG Test Access Port (TAP)☆39Jul 17, 2014Updated 11 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- CORE-V Family of RISC-V Cores☆357Mar 31, 2026Updated 2 months ago
- ☆36Nov 4, 2024Updated last year
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆20Nov 26, 2024Updated last year
- Documentation and status of UEFI on RISC-V☆64Aug 25, 2021Updated 4 years ago
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆187Apr 4, 2026Updated 2 months ago
- The OpenPiton Platform☆31May 22, 2023Updated 3 years ago
- ☆38Jun 8, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A collection of mesh routing protocols.☆29Jul 24, 2025Updated 10 months ago
- ☆155Oct 6, 2023Updated 2 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- ☆15Nov 8, 2019Updated 6 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆294Updated this week
- ☆91Aug 26, 2025Updated 9 months ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 3 years ago