openhwgroup / core-v-xifLinks
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
☆76Updated last year
Alternatives and similar repositories for core-v-xif
Users that are interested in core-v-xif are comparing it to the libraries listed below
Sorting:
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- Generic Register Interface (contains various adapters)☆133Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- The multi-core cluster of a PULP system.☆109Updated last month
- RISC-V Verification Interface☆126Updated last week
- ☆115Updated 3 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆125Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆189Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- RISC-V System on Chip Template☆159Updated 3 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- RISC-V Nox core☆69Updated 4 months ago
- RISC-V soft-core microcontroller for FPGA implementation☆187Updated last week
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆115Updated 4 months ago
- Simple runtime for Pulp platforms☆49Updated 3 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 3 weeks ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆117Updated 4 years ago
- ☆97Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆151Updated last year