This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
☆206Jun 10, 2026Updated this week
Alternatives and similar repositories for core-v-mcu
Users that are interested in core-v-mcu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆160Oct 31, 2024Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆226Jan 11, 2026Updated 5 months ago
- Functional verification project for the CORE-V family of RISC-V cores.☆685May 27, 2026Updated 2 weeks ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆271Nov 6, 2024Updated last year
- pulp_soc is the core building component of PULP based SoCs☆84Mar 10, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,247May 29, 2026Updated 2 weeks ago
- VeeR EL2 Core☆338Jun 5, 2026Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆133Jul 11, 2025Updated 11 months ago
- CORE-V Family of RISC-V Cores☆355Mar 31, 2026Updated 2 months ago
- Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board☆15Nov 16, 2022Updated 3 years ago
- The multi-core cluster of a PULP system.☆114Updated this week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,918Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆341Dec 11, 2024Updated last year
- VeeR EH1 core☆949May 29, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆483May 8, 2026Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆37Updated this week
- RISC-V Verification Interface☆153Jun 8, 2026Updated last week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆230Nov 22, 2023Updated 2 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆341Updated this week
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆275Updated this week
- Main Repo for the OpenHW Group Software Task Group☆17Mar 11, 2025Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆669May 11, 2026Updated last month
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆559Nov 26, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- ☆14Nov 8, 2023Updated 2 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆613May 26, 2026Updated 3 weeks ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆62Apr 3, 2026Updated 2 months ago
- Common SystemVerilog components☆757Jun 5, 2026Updated last week
- ☆36Mar 8, 2023Updated 3 years ago
- ☆265Dec 22, 2022Updated 3 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,969Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated last month
- An open-source microcontroller system based on RISC-V☆1,040Feb 6, 2024Updated 2 years ago
- Tile based architecture designed for computing efficiency, scalability and generality☆294Updated this week
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆20Jun 3, 2026Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆311Apr 1, 2026Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆308Oct 17, 2023Updated 2 years ago