Alternatives and similar repositories for core-v-mcu

Users that are interested in core-v-mcu are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated this week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆287Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆310Updated 10 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆332Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆249Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆221Updated last month
• chipsalliance / Cores-VeeR-EH2
  ☆250Updated 2 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆278Updated 5 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆162Updated 6 years ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆307Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆132Updated last week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 4 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆97Updated 4 months ago
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• chipsalliance / VeeR-ISS
  ☆150Updated 2 years ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆159Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆369Updated 9 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆129Updated 2 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆175Updated this week
• pulp-platform / pulp-sdk
  ☆121Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆400Updated 5 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆133Updated last month
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated 2 years ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆232Updated this week
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆151Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆133Updated 7 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last week