openhwgroup / core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
☆172Updated last year
Alternatives and similar repositories for core-v-mcu:
Users that are interested in core-v-mcu are comparing it to the libraries listed below
- VeeR EL2 Core☆263Updated this week
- RISC-V Debug Support for our PULP RISC-V Cores☆243Updated 3 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆226Updated 3 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆205Updated last week
- CORE-V Family of RISC-V Cores☆229Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆306Updated 2 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆224Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆264Updated 4 years ago
- ☆225Updated 2 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆142Updated 3 months ago
- RISC-V Verification Interface☆84Updated 5 months ago
- Basic RISC-V Test SoC☆112Updated 5 years ago
- Generic Register Interface (contains various adapters)☆107Updated 4 months ago
- RISC-V System on Chip Template☆156Updated this week
- Instruction Set Generator initially contributed by Futurewei☆272Updated last year
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆82Updated 3 weeks ago
- ☆275Updated last week
- Common SystemVerilog components☆572Updated 2 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆491Updated last week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆455Updated last week
- An Open-Source Design and Verification Environment for RISC-V☆78Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆67Updated 10 months ago
- Verilog Configurable Cache☆170Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆221Updated 3 months ago
- RISC-V CPU Core☆308Updated 8 months ago
- ☆129Updated last year
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆310Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- A Fast, Low-Overhead On-chip Network☆169Updated last week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆204Updated 4 years ago