FuseSoC-based SoC for VeeR EH1 and EL2
☆343Dec 11, 2024Updated last year
Alternatives and similar repositories for VeeRwolf
Users that are interested in VeeRwolf are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VeeR EH1 core☆968Jul 16, 2026Updated 2 months ago
- VeeR EL2 Core☆344Updated this week
- VeeR EH2 core☆280Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 8 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,461Sep 12, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,291Aug 26, 2026Updated 3 weeks ago
- FuseSoC standard core library☆172Aug 19, 2026Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated last year
- CORE-V Family of RISC-V Cores☆371Mar 31, 2026Updated 5 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆281Nov 6, 2024Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Sep 14, 2026Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆328Updated this week
- Functional verification project for the CORE-V family of RISC-V cores.☆723Updated this week
- SERV - The SErial RISC-V CPU☆1,887Aug 25, 2026Updated 3 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆158Oct 6, 2023Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Dec 10, 2019Updated 6 years ago
- Generic Register Interface (contains various adapters)☆140Aug 6, 2026Updated last month
- An abstraction library for interfacing EDA tools☆795Updated this week
- A Linux-capable RISC-V multicore for and by the world☆832Updated this week
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,002Nov 15, 2024Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆367Updated this week
- Common SystemVerilog components☆799Updated this week
- 32-bit Superscalar RISC-V CPU☆1,309Sep 18, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- RISC-V CPU Core☆450Jun 24, 2025Updated last year
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆547Aug 19, 2026Updated last month
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,702Updated this week
- pulp_soc is the core building component of PULP based SoCs☆86Jul 17, 2026Updated 2 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,267Updated this week
- The multi-core cluster of a PULP system.☆116Aug 4, 2026Updated last month
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,123Updated this week
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,063Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- BaseJump STL: A Standard Template Library for SystemVerilog☆681Sep 8, 2026Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- Random instruction generator for RISC-V processor verification☆1,357Sep 4, 2026Updated 2 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆212Sep 2, 2026Updated 2 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,384Sep 7, 2026Updated 2 weeks ago
- The OpenPiton Platform☆828Feb 25, 2026Updated 6 months ago
- Rocket Chip Generator☆3,869Sep 13, 2026Updated last week