chipsalliance / VeeRwolfLinks
FuseSoC-based SoC for VeeR EH1 and EL2
☆334Updated last year
Alternatives and similar repositories for VeeRwolf
Users that are interested in VeeRwolf are comparing it to the libraries listed below
Sorting:
- VeeR EL2 Core☆315Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆291Updated last month
- ☆258Updated 3 years ago
- RISC-V CPU Core☆405Updated 7 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆195Updated last month
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆561Updated 3 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆456Updated 8 months ago
- CORE-V Family of RISC-V Cores☆318Updated 11 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆284Updated 5 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆255Updated last year
- Functional verification project for the CORE-V family of RISC-V cores.☆648Updated 2 weeks ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆316Updated last week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Updated 2 weeks ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆223Updated 5 years ago
- Instruction Set Generator initially contributed by Futurewei☆304Updated 2 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆536Updated last year
- Common SystemVerilog components☆700Updated last month
- RISC-V microcontroller for embedded and FPGA applications☆190Updated this week
- Code used in☆201Updated 8 years ago
- Verilog Configurable Cache☆192Updated this week
- ☆305Updated last week
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆376Updated 11 months ago
- ☆365Updated 4 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆641Updated last week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆400Updated 3 months ago
- Bus bridges and other odds and ends☆631Updated 9 months ago
- RISC-V Torture Test☆211Updated last year
- Ariane is a 6-stage RISC-V CPU☆153Updated 6 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆239Updated last year