Alternatives and similar repositories for VeeRwolf

Users that are interested in VeeRwolf are comparing it to the libraries listed below

• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated last week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆272Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆240Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆359Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆283Updated 5 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆182Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆569Updated 3 weeks ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆512Updated 5 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆436Updated 2 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆637Updated last week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆271Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆217Updated 2 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆343Updated 5 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆240Updated 8 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆138Updated 6 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆505Updated 8 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆593Updated last week
• SpinalHDL / NaxRiscv
  ☆293Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆576Updated 3 months ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆175Updated 3 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆293Updated last week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆180Updated 7 months ago
• ucb-bar / berkeley-hardfloat
  ☆334Updated 10 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆653Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆278Updated 11 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year