chipsalliance / VeeRwolfLinks
FuseSoC-based SoC for VeeR EH1 and EL2
☆321Updated 7 months ago
Alternatives and similar repositories for VeeRwolf
Users that are interested in VeeRwolf are comparing it to the libraries listed below
Sorting:
- VeeR EL2 Core☆288Updated 2 weeks ago
- ☆239Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆260Updated 2 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆510Updated 5 months ago
- RISC-V CPU Core☆348Updated 2 weeks ago
- Functional verification project for the CORE-V family of RISC-V cores.☆563Updated last week
- Common SystemVerilog components☆634Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆181Updated 2 weeks ago
- CORE-V Family of RISC-V Cores☆277Updated 4 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆271Updated 4 years ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆271Updated this week
- Instruction Set Generator initially contributed by Futurewei☆289Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆216Updated 4 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆239Updated 8 months ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆429Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆585Updated last month
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆333Updated 4 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆217Updated last month
- Verilog Configurable Cache☆179Updated 7 months ago
- Bus bridges and other odds and ends☆572Updated 2 months ago
- SystemVerilog to Verilog conversion☆645Updated 2 weeks ago
- ☆291Updated last week
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 7 months ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆503Updated 7 months ago
- lowRISC Style Guides☆440Updated last month
- RISC-V Torture Test☆196Updated last year
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆290Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆332Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆377Updated this week
- RISC-V microcontroller IP core developed in Verilog☆174Updated 3 months ago