Alternatives and similar repositories for core-v-sw

Users that are interested in core-v-sw are comparing it to the libraries listed below

• riscvarchive / riscv-edk2-platforms
  Port of EDK2 implementation of UEFI to RISC-V. See documentation at:
  ☆18Updated 3 years ago
• litex-hub / zephyr-on-litex-vexriscv
  ☆12Updated 8 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• openhwgroup / cv32e40x-dv
  CV32E40X Design-Verification environment
  ☆12Updated last year
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• XUANTIE-RV / xuantie-yocto
  Yocto project for Xuantie RISC-V CPU
  ☆38Updated 2 weeks ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 2 months ago
• riscv-admin / riscv-landscape
  🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…
  ☆15Updated this week
• vortexgpgpu / pocl
  a clone of POCL that includes RISC-V newlib devices support and Vortex
  ☆42Updated 2 months ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆46Updated 9 months ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆36Updated 2 months ago
• riscv / riscv-smbios
  RISC-V SMBIOS Type 44 Spec
  ☆12Updated last year
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆38Updated 7 months ago
• riscvarchive / riscv-zfinx
  ☆12Updated last year
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• LLNL / zhw
  ZFP Hardware Implementation
  ☆13Updated 2 years ago
• spacemonkeydelivers / riscv_security_contest_project
  ☆9Updated 2 years ago
• pulp-platform / hero-sdk
  ⛔ DEPRECATED ⛔ HERO Software Development Kit
  ☆20Updated 3 years ago
• sifiveinc / meta-sifive
  SiFive OpenEmbedded / Yocto BSP Layer
  ☆52Updated last week
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Updated 5 years ago
• riscv-non-isa / riscv-uefi
  ☆29Updated 3 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆19Updated last year
• RCSL-HKUST / heterosim
  HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…
  ☆21Updated 8 years ago