nietzhuang / Cycle-accurate-Eyeriss-modelLinks
A scalable Eyeriss model in SystemC.
☆33Updated 3 years ago
Alternatives and similar repositories for Cycle-accurate-Eyeriss-model
Users that are interested in Cycle-accurate-Eyeriss-model are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆39Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- Template for project1 TPU☆23Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆79Updated 2 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- ☆29Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- Ratatoskr NoC Simulator☆29Updated 4 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Updated 6 years ago
- ☆38Updated 3 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 3 years ago
- ☆40Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆20Updated 8 months ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- ☆72Updated 7 years ago
- ☆58Updated 6 years ago
- ☆35Updated 6 years ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- ☆63Updated 9 months ago
- ☆36Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- ☆15Updated 3 years ago
- A small Neural Network Processor for Edge devices.☆15Updated 3 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- ☆49Updated 6 years ago