Alternatives and similar repositories for AXI_DMA_CONTROLLER

Users that are interested in AXI_DMA_CONTROLLER are comparing it to the libraries listed below

• open-dv / dma_axi
  ☆16Updated 6 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• fangyzh26 / FIFO
  包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）
  ☆20Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆15Updated last year
• mfkiwl / E203_dma
  ☆10Updated 5 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆20Updated 2 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆45Updated this week
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆13Updated 2 years ago
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆14Updated 3 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆13Updated 2 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆23Updated last year
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆12Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆17Updated 4 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆13Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 10 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆50Updated 3 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• kumarswamy12 / ROUTER-1-3
  verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
  ☆13Updated 6 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 9 years ago
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated last year