Jefferyy-Peng / AXI_DMA_CONTROLLER
☆10Updated last year
Related projects ⓘ
Alternatives and complementary repositories for AXI_DMA_CONTROLLER
- ☆16Updated last year
- ☆16Updated 5 years ago
- verification of simple axi-based cache☆17Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆14Updated 4 months ago
- Implementation of the PCIe physical layer☆29Updated 4 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆12Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆10Updated 3 years ago
- ☆9Updated 4 years ago
- ☆17Updated 9 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆31Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆17Updated 5 years ago
- ☆18Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago
- ☆21Updated 3 years ago
- UVM Testbench for synchronus fifo☆15Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- 异步FIFO的内部实现☆24Updated 6 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 6 years ago
- ☆33Updated 2 years ago
- ☆14Updated 2 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- 位宽和深度可定制的异步FIFO☆12Updated 5 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆30Updated last year
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago