☆13Mar 10, 2023Updated 3 years ago
Alternatives and similar repositories for AXI_DMA_CONTROLLER
Users that are interested in AXI_DMA_CONTROLLER are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆21Nov 18, 2022Updated 3 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- AXI DMA 32 / 64 bits☆128Jul 17, 2014Updated 12 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- A scalable Eyeriss model in SystemC.☆36Jan 1, 2023Updated 3 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year
- ☆16Dec 4, 2021Updated 4 years ago
- ARTICo³ - Dynamic and Partially Reconfigurable Architecture for Run-Time Adaptive, High Performance Embedded Computing☆12Sep 10, 2024Updated 2 years ago
- ☆19Aug 22, 2022Updated 4 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆40Oct 25, 2020Updated 5 years ago
- ☆22Sep 26, 2025Updated last year
- ☆18Apr 5, 2015Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 4 years ago
- System Verilog based RTL design of DMA controller for 8086 microprocessor based systems.☆30Mar 30, 2020Updated 6 years ago
- ☆19Aug 11, 2022Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆40Dec 22, 2023Updated 2 years ago
- Testing greedy algorithms OMP and COSAMP using structured sparsity☆11May 24, 2021Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆19Jul 29, 2014Updated 12 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- ☆18Jun 29, 2026Updated 2 months ago
- ☆13Nov 13, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 3 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 7 years ago
- NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks☆21Feb 22, 2023Updated 3 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 4 years ago
- ☆24Jun 30, 2025Updated last year
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆16Dec 29, 2016Updated 9 years ago
- Image Reconstruction Using Compressive Sensing☆22Dec 17, 2019Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆45Aug 10, 2022Updated 4 years ago
- An 8 input interrupt controller written in Verilog.☆31Mar 22, 2012Updated 14 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Discover, setup, and get stats on network interfaces☆11Nov 17, 2023Updated 2 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago
- ☆10Nov 4, 2022Updated 3 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- OmpSs Examples and Exercises☆14Jun 28, 2019Updated 7 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆36Jul 4, 2024Updated 2 years ago