frobino / Nostrum-SystemC-simulatorLinks
SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
☆14Updated 11 years ago
Alternatives and similar repositories for Nostrum-SystemC-simulator
Users that are interested in Nostrum-SystemC-simulator are comparing it to the libraries listed below
Sorting:
- ☆13Updated 9 months ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- Network on Chip for MPSoC☆28Updated 3 weeks ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆18Updated 2 years ago
- ☆32Updated 2 weeks ago
- Direct Access Memory for MPSoC☆13Updated 3 weeks ago
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- ☆13Updated 6 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- ☆20Updated last month
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆30Updated last year
- ☆10Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆18Updated 7 years ago
- ☆22Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Updated 11 years ago
- ☆16Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆26Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆17Updated 8 months ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- ☆12Updated 10 years ago
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 9 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 9 months ago