frobino / Nostrum-SystemC-simulator
SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
☆13Updated 10 years ago
Alternatives and similar repositories for Nostrum-SystemC-simulator:
Users that are interested in Nostrum-SystemC-simulator are comparing it to the libraries listed below
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 5 years ago
- ☆11Updated 10 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆12Updated 9 years ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 6 months ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Direct Access Memory for MPSoC☆12Updated 3 weeks ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- Network on Chip for MPSoC☆25Updated 3 weeks ago
- ☆25Updated 4 years ago
- ☆16Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated 3 weeks ago
- ☆12Updated 9 years ago
- CORE-V MCU UVM Environment and Test Bench☆18Updated 5 months ago
- Archives of SystemC from The Ground Up Book Exercises☆29Updated 2 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆14Updated 4 months ago
- ☆24Updated 5 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- Ratatoskr NoC Simulator☆22Updated 3 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- My local copy of UVM-SystemC☆11Updated 8 months ago
- RISC-V IOMMU in verilog☆16Updated 2 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- ☆21Updated last week
- Manycore platform Simulation tool for NoC-based platform at a Transactional Level Modeling level☆10Updated 8 years ago
- SoC Based on ARM Cortex-M3☆25Updated this week
- ☆12Updated 7 years ago