☆10Oct 8, 2021Updated 4 years ago
Alternatives and similar repositories for chipyard
Users that are interested in chipyard are comparing it to the libraries listed below
Sorting:
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆19Dec 29, 2024Updated last year
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆19Apr 17, 2021Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆33Aug 13, 2024Updated last year
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- ☆60Aug 30, 2021Updated 4 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆33Jan 1, 2023Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Dec 2, 2021Updated 4 years ago
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆34Feb 11, 2026Updated 2 weeks ago
- Penn CIS 5650 (GPU Programming and Architecture) Final Project☆44Dec 11, 2023Updated 2 years ago
- A comparison of various moving window median algorithms☆17Jun 4, 2011Updated 14 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆12Aug 9, 2019Updated 6 years ago
- Network on chip based neural network accelerator☆10Mar 25, 2021Updated 4 years ago
- Code repository for experiments in SpecROP paper☆13Sep 3, 2021Updated 4 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- 基于FPGA的FFT算法并行优化☆12Mar 7, 2024Updated last year
- FlappyBird愤怒的小鸟 c++游戏实现 学习代码☆10Nov 16, 2018Updated 7 years ago
- Fast and thread safe C++11 implementation of of the Aho-Corasick algorithm.☆10Mar 4, 2020Updated 5 years ago
- A simple 8086-CPU simulator using Verilog and Quartus II☆10Jul 9, 2018Updated 7 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆21Jun 30, 2025Updated 8 months ago
- A memory allocator that aims to eliminate dangling pointer vulnerabilities at a low overhead, using virtualisation via Dune. My Computer …☆10Nov 27, 2019Updated 6 years ago
- VMSDK implements the Evidence API☆11Nov 25, 2024Updated last year
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 9 months ago
- Linux integrity monitoring for CentOS/RHEL☆12May 13, 2020Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆126Jan 20, 2025Updated last year
- ☆37Nov 11, 2018Updated 7 years ago
- eyeriss-chisel3☆40May 2, 2022Updated 3 years ago
- PKU computer organization and architecture RISC-V Simulator LAB☆37Sep 18, 2018Updated 7 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 6 years ago
- An experimental modular OS written in Rust.☆12Jul 19, 2024Updated last year
- The implementation of our IEEE S&P 2024 paper "Securely Fine-tuning Pre-trained Encoders Against Adversarial Examples".☆11Jun 28, 2024Updated last year
- This is the repository for the code and artifacts related to the CCS2022 paper: C2C: Fine-grained Configuration-driven System Call Filter…☆11Nov 4, 2022Updated 3 years ago
- Hypervisor from scratch in linux☆13May 8, 2022Updated 3 years ago
- ☆14Dec 1, 2020Updated 5 years ago
- A Rust-based Unikernel Enhancing Reliability and Efficiency of Embedded Systems.☆11Jun 28, 2024Updated last year
- EFI driver which disables Virtualization-based Security (VBS) in Microsoft Windows☆18Aug 1, 2024Updated last year
- Author Profiling for Abuse Detection (COLING 2018)☆10Dec 8, 2022Updated 3 years ago