hyoukjun / microswitch-nocLinks
☆27Updated 5 years ago
Alternatives and similar repositories for microswitch-noc
Users that are interested in microswitch-noc are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆52Updated 8 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- Template for project1 TPU☆19Updated 4 years ago
- ☆15Updated 3 years ago
- ☆34Updated 4 months ago
- Project repo for the POSH on-chip network generator☆50Updated 6 months ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- ☆36Updated 6 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last month
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Public release☆56Updated 6 years ago
- ☆17Updated 4 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- ☆27Updated last year
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆21Updated 9 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago