hyoukjun / microswitch-nocLinks
☆27Updated 5 years ago
Alternatives and similar repositories for microswitch-noc
Users that are interested in microswitch-noc are comparing it to the libraries listed below
Sorting:
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆21Updated 12 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated this week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Project repo for the POSH on-chip network generator☆49Updated 4 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- ☆34Updated 6 years ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated 2 years ago
- CNN accelerator☆27Updated 8 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Algorithmic C Machine Learning Library☆26Updated 7 months ago
- ☆29Updated 4 years ago
- ☆26Updated last year
- ☆30Updated 2 weeks ago
- DUTH RISC-V Microprocessor☆20Updated 8 months ago
- General Purpose AXI Direct Memory Access☆55Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- ☆14Updated 2 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 5 months ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆30Updated 6 years ago
- A verilog implementation for Network-on-Chip☆75Updated 7 years ago