Alternatives and similar repositories for Systolic-Array

Users that are interested in Systolic-Array are comparing it to the libraries listed below

• hyoukjun / microswitch-noc
  ☆29Updated 6 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆82Updated 2 months ago
• kiabuzz / CompressedLUT
  A tool to generate optimized hardware files for univariate functions.
  ☆29Updated last year
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆21Updated 3 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆23Updated 4 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆29Updated 8 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆48Updated last month
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆36Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• CMU-SAFARI / CLRDRAM
  Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…
  ☆14Updated 5 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆33Updated 3 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆30Updated last month
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆73Updated 3 years ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆46Updated last year
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆56Updated 8 years ago
• ucb-bar / gemmini-rocc-tests
  Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
  ☆62Updated 7 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated last month
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 10 months ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆15Updated 11 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• hyoukjun / DesignCNNAccelerators
  Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
  ☆32Updated 7 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆32Updated 2 years ago
• mohsaied / rtl2booksim
  Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
  ☆25Updated 10 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆12Updated 2 years ago