KyleParkJong / Network-on-Chip-SimulatorLinks
Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
☆31Updated last year
Alternatives and similar repositories for Network-on-Chip-Simulator
Users that are interested in Network-on-Chip-Simulator are comparing it to the libraries listed below
Sorting:
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆59Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆31Updated 7 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆64Updated 2 weeks ago
- ☆17Updated 4 months ago
- ☆27Updated 5 years ago
- ☆34Updated 4 months ago
- A systolic array matrix multiplier☆25Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆29Updated 2 years ago
- Template for project1 TPU☆19Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆37Updated 6 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- ☆12Updated last year
- ☆49Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 3 months ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆23Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- cycle accurate Network-on-Chip Simulator☆30Updated 2 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆66Updated last week
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆59Updated 3 years ago
- ☆35Updated 6 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆43Updated 9 months ago
- ☆36Updated 6 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year