karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator
☆159Updated 5 years ago
Alternatives and similar repositories for CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
Users that are interested in CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2 are comparing it to the libraries listed below
Sorting:
- ☆110Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆179Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆109Updated this week
- Convolutional accelerator kernel, target ASIC & FPGA☆196Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆66Updated 2 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆100Updated 4 years ago
- IC implementation of Systolic Array for TPU☆239Updated 6 months ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆74Updated last year
- verilog实现systolic array及配套IO☆8Updated 5 months ago
- Verilog implementation of Softmax function☆65Updated 2 years ago
- ☆64Updated 6 years ago
- IC implementation of TPU☆124Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆150Updated 10 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆36Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆148Updated this week
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- ☆38Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆172Updated last year
- AXI总线连接器☆97Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆31Updated 4 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆11Updated 9 months ago