Alternatives and similar repositories for EyerissSimulator:

Users that are interested in EyerissSimulator are comparing it to the libraries listed below

• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆52Updated 2 weeks ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆38Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 3 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• GATECH-EIC / AutoDNNchip
  ☆70Updated 5 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆49Updated last month
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆43Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆71Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆99Updated 5 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆51Updated last week
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆76Updated 3 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆40Updated last year
• fffasttime / AnyPackingNet
  ☆26Updated last month
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆56Updated 3 years ago
• maestro-project / gamma-timeloop
  ☆14Updated last year
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆35Updated 4 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 9 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆45Updated 2 months ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆26Updated last year
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• GraphSAINT / GNN-ARCH
  [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
  ☆41Updated 4 years ago
• iitm-sysdl / FuSeConv
  Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021
  ☆14Updated 3 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆51Updated last month