Alternatives and similar repositories for systemc-chisel-tools

Users that are interested in systemc-chisel-tools are comparing it to the libraries listed below

• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• maltanar / spmvaccsim
  A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.
  ☆15Updated 11 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last week
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated 2 weeks ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆34Updated 9 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 11 months ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• jkorinth / chisel-packaging
  IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.
  ☆11Updated 7 years ago
• pulp-platform / axi_llc
  ☆33Updated last month
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆18Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• StanfordVLSI / FP-Gen
  FPU Generator
  ☆20Updated 4 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated 2 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆52Updated 5 months ago
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆13Updated 6 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆56Updated 8 years ago
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆17Updated this week
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆18Updated 6 years ago