IronySuzumiya / NiuDianNaoLinks
A simple cycle-accurate DaDianNao simulator
☆13Updated 6 years ago
Alternatives and similar repositories for NiuDianNao
Users that are interested in NiuDianNao are comparing it to the libraries listed below
Sorting:
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- ☆36Updated 4 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆30Updated 2 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- ☆36Updated 6 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆22Updated 7 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆29Updated 2 years ago
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆25Updated 10 months ago
- ☆15Updated last year
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 8 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- Fibertree emulator☆14Updated 11 months ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- ☆27Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- ☆72Updated 2 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- ☆25Updated last year
- Learn NVDLA by SOMNIA☆43Updated 5 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆20Updated last year
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated 2 weeks ago