IronySuzumiya / NiuDianNaoLinks
A simple cycle-accurate DaDianNao simulator
☆13Updated 6 years ago
Alternatives and similar repositories for NiuDianNao
Users that are interested in NiuDianNao are comparing it to the libraries listed below
Sorting:
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- ☆36Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- Domain-Specific Architecture Generator 2☆21Updated 3 years ago
- A scalable Eyeriss model in SystemC.☆31Updated 2 years ago
- Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube☆12Updated 8 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆15Updated last year
- ☆36Updated 7 months ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of follow…☆25Updated 10 months ago
- ☆25Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube☆23Updated 7 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆43Updated 8 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- ☆72Updated 2 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13Updated 9 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆60Updated 3 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆58Updated 3 weeks ago
- NeuraChip Accelerator Simulator☆14Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆82Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆44Updated 10 months ago
- Fibertree emulator☆15Updated last year