Alternatives and similar repositories for NiuDianNao

Users that are interested in NiuDianNao are comparing it to the libraries listed below

• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆14Updated 5 years ago
• estwings57 / HMC-MAC
  Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube
  ☆11Updated 8 years ago
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• OSU-STARLAB / GPGPU-Ramulator-Simulator
  Replace original DRAM model in GPGPU-sim with Ramulator DRAM model
  ☆18Updated 6 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆29Updated 3 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆45Updated 3 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆20Updated 2 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆28Updated last year
• suchandler96 / gem5-NVDLA
  ☆30Updated last month
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 6 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆23Updated 2 years ago
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆21Updated 6 years ago
• gicLAB / SECDA
  ☆22Updated 2 years ago
• UIUC-ChenLab / rip
  ☆16Updated 7 years ago
• jinhachung / tptpu-sim
  A Toy-Purpose TPU Simulator
  ☆18Updated 11 months ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆20Updated 3 years ago
• union-codesign / union
  ☆14Updated 3 years ago
• maestro-project / gamma-timeloop
  ☆14Updated last year
• aravinds92 / Systolic-Array
  Systolic array based hardware for Image processing on the SPARTAN-6 FPGA
  ☆12Updated 8 years ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆11Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆26Updated last year
• georgia-tech-synergy-lab / hardtaco-hls
  HLS project modeling various sparse accelerators.
  ☆12Updated 3 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆18Updated last week
• priyanka-raina / dnn-accelerator
  ☆13Updated 4 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆19Updated last year
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 5 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆35Updated 4 years ago
• he-actlab / polymath
  ☆21Updated 2 months ago