muneebullashariff / pulpino_soc_uvm_testbenchLinks
UVM testbench for verifying the Pulpino SoC
☆14Updated 5 years ago
Alternatives and similar repositories for pulpino_soc_uvm_testbench
Users that are interested in pulpino_soc_uvm_testbench are comparing it to the libraries listed below
Sorting:
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- UVM Clock and Reset Agent☆13Updated 8 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago
- ☆12Updated 9 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- ☆26Updated 4 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- ☆13Updated 7 months ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆16Updated 6 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Updated 7 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆34Updated 4 months ago
- ☆15Updated 6 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- System on Chip verified with UVM/OSVVM/FV☆31Updated 4 months ago
- ☆29Updated 2 weeks ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- APB Logic☆19Updated last month
- NoC based MPSoC☆11Updated 11 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Updated 5 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago