dcblack / ModernSystemC
Example code for Modern SystemC using Modern C++
☆61Updated 2 years ago
Alternatives and similar repositories for ModernSystemC:
Users that are interested in ModernSystemC are comparing it to the libraries listed below
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆102Updated 2 weeks ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆56Updated 2 weeks ago
- SystemC training aimed at TLM.☆28Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆24Updated 2 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Learn systemC with examples☆108Updated 2 years ago
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆16Updated 11 years ago
- ☆25Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- Project repo for the POSH on-chip network generator☆44Updated last year
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- ☆41Updated 6 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A repository for SystemC Learning examples☆67Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- Public release☆49Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- ☆71Updated 10 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated this week
- ☆25Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆60Updated 8 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- Algorithmic C Machine Learning Library☆22Updated 2 months ago