PolyArch / fp-diannaoLinks
☆14Updated 5 months ago
Alternatives and similar repositories for fp-diannao
Users that are interested in fp-diannao are comparing it to the libraries listed below
Sorting:
- ☆15Updated last year
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆34Updated 6 years ago
- ☆71Updated 5 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆52Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆20Updated 5 years ago
- ☆36Updated 4 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- A scalable Eyeriss model in SystemC.☆29Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- Learn NVDLA by SOMNIA☆43Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆57Updated 5 months ago
- ☆60Updated 5 years ago
- ☆23Updated 3 years ago
- ☆46Updated 5 years ago
- ☆12Updated last year
- ☆35Updated 5 years ago
- ☆17Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated last year
- ☆37Updated 6 months ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆12Updated 9 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago