PolyArch / fp-diannaoLinks
☆14Updated 6 months ago
Alternatives and similar repositories for fp-diannao
Users that are interested in fp-diannao are comparing it to the libraries listed below
Sorting:
- ☆71Updated 5 years ago
- ☆15Updated last year
- ☆23Updated 4 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆10Updated 6 years ago
- ☆36Updated 4 years ago
- ☆35Updated 6 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- A scalable Eyeriss model in SystemC.☆30Updated 2 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆52Updated last year
- A Toy-Purpose TPU Simulator☆19Updated last year
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Updated 3 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- ☆46Updated 5 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 3 years ago
- Learn NVDLA by SOMNIA☆43Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆20Updated 3 years ago
- ☆59Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 2 years ago
- ☆15Updated 2 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 4 years ago