PolyArch / fp-diannaoLinks
☆14Updated 9 months ago
Alternatives and similar repositories for fp-diannao
Users that are interested in fp-diannao are comparing it to the libraries listed below
Sorting:
- ☆15Updated 2 years ago
- ☆71Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆35Updated 6 years ago
- ☆36Updated 4 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- Eyeriss chip simulator☆39Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆32Updated 3 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Updated last year
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Updated 6 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 10 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆16Updated 6 years ago
- ☆23Updated 4 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆62Updated 2 months ago
- ☆39Updated 3 weeks ago
- A Toy-Purpose TPU Simulator☆21Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- BlockCIrculantRNN (LSTM and GRU) using TensorFlow☆14Updated 7 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Updated 3 years ago
- Learn NVDLA by SOMNIA☆42Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆27Updated 5 years ago
- ☆72Updated 2 years ago
- ☆16Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Updated 5 years ago