PolyArch / fp-diannao
☆14Updated last year
Alternatives and similar repositories for fp-diannao:
Users that are interested in fp-diannao are comparing it to the libraries listed below
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆17Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 5 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 2 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Learn NVDLA by SOMNIA☆32Updated 5 years ago
- ☆14Updated 5 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆26Updated last month
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆45Updated 10 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- Fibertree emulator☆12Updated 3 months ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 5 years ago
- ☆20Updated 2 years ago
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆22Updated 3 years ago
- ☆32Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- ☆23Updated 3 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆20Updated last month
- ☆14Updated last year
- ☆69Updated 4 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆22Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- ☆33Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆61Updated 3 years ago
- BlockCIrculantRNN (LSTM and GRU) using TensorFlow☆14Updated 6 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆32Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago