PolyArch / fp-diannaoLinks
☆14Updated 4 months ago
Alternatives and similar repositories for fp-diannao
Users that are interested in fp-diannao are comparing it to the libraries listed below
Sorting:
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆51Updated last year
- ☆71Updated 5 years ago
- ☆36Updated 4 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- A scalable Eyeriss model in SystemC.☆28Updated 2 years ago
- ☆15Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- ☆34Updated 6 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆20Updated 5 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- A simple cycle-accurate DaDianNao simulator☆13Updated 6 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆16Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- ☆46Updated 5 years ago
- ☆72Updated 2 years ago
- ☆23Updated 3 years ago
- ☆25Updated 2 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆22Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago