asinghani / pifive-cpuLinks
RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator
☆10Updated 4 years ago
Alternatives and similar repositories for pifive-cpu
Users that are interested in pifive-cpu are comparing it to the libraries listed below
Sorting:
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- Wraps the NVDLA project for Chipyard integration☆22Updated 5 months ago
- ☆20Updated last month
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- Wrapper for ETH Ariane Core☆22Updated 5 months ago
- A configurable general purpose graphics processing unit for☆12Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 6 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- An Open Source Link Protocol and Controller☆28Updated 4 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Updated 3 years ago
- Theia: ray graphic processing unit☆20Updated 11 years ago
- ☆14Updated 11 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Updated 3 weeks ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆28Updated last week
- A coverage library for Chisel designs☆11Updated 5 years ago
- NoC based MPSoC☆11Updated 11 years ago
- ☆33Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆20Updated 9 months ago
- UVM testbench for verifying the Pulpino SoC☆13Updated 5 years ago
- ☆13Updated 2 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 11 years ago
- ☆24Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Useful utilities for BAR projects☆32Updated 2 years ago
- ☆90Updated last month
- Wrappers for open source FPU hardware implementations.☆37Updated 2 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago