Alternatives and similar repositories for DNN-Chip-Predictor

Users that are interested in DNN-Chip-Predictor are comparing it to the libraries listed below

• maestro-project / gamma
  ☆42Updated last year
• isakedo / DNNsim
  ☆35Updated 5 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆62Updated 2 months ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆60Updated 4 years ago
• fffasttime / AnyPackingNet
  ☆31Updated 8 months ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• maestro-project / gamma-timeloop
  ☆15Updated 2 years ago
• CASR-HKU / DPACS
  ☆18Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆45Updated 3 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆43Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 4 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆38Updated 4 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆49Updated 10 months ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆36Updated 3 years ago
• PSCLab-ASU / Systolic-CNN
  ☆17Updated 4 years ago
• CASR-HKU / AGNA-FCCM2023
  ☆12Updated 2 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆64Updated 5 months ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• maestro-project / AIrchitect-v2
  [DATE 2025] Official implementation and dataset of AIrchitect v2: Learning the Hardware Accelerator Design Space through Unified Represen…
  ☆18Updated 11 months ago
• cornell-zhang / FracBNN
  FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
  ☆95Updated 4 years ago
• harvard-acc / EdgeBERT
  HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference
  ☆53Updated last year
• maestro-project / confuciux
  ☆32Updated 4 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆39Updated 5 years ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆54Updated 2 years ago
• jha-lab / codebench
  [TECS'23] A project on the co-design of Accelerators and CNNs.
  ☆21Updated 3 years ago