GATECH-EIC / DNN-Chip-Predictor
[ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures
☆23Updated 2 years ago
Alternatives and similar repositories for DNN-Chip-Predictor:
Users that are interested in DNN-Chip-Predictor are comparing it to the libraries listed below
- ☆19Updated 2 years ago
- ☆32Updated 4 years ago
- ☆14Updated last year
- ☆39Updated 8 months ago
- ☆26Updated 11 months ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆36Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆37Updated 2 years ago
- ☆26Updated 3 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆50Updated 2 weeks ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A general framework for optimizing DNN dataflow on systolic array☆34Updated 4 years ago
- ☆70Updated 5 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- ☆23Updated 3 years ago
- ☆33Updated 3 years ago
- ☆33Updated 6 years ago
- ☆15Updated 4 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆38Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆43Updated 2 years ago
- ☆19Updated 4 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- ☆10Updated 5 months ago
- Implementation of Input Stationary, Weight Stationary and Output Stationary dataflow for given neural network on a tiled architecture☆9Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated last month
- ☆71Updated 2 years ago
- ☆16Updated 2 years ago