Alternatives and similar repositories for PAT-Noxim

Users that are interested in PAT-Noxim are comparing it to the libraries listed below

• suchandler96 / gem5-NVDLA
  ☆40Updated 8 months ago
• sfu-arch / SpGEMM
  ☆36Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆55Updated 8 years ago
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆44Updated 11 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆71Updated 2 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆71Updated 2 weeks ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆45Updated 8 years ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆36Updated last month
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆35Updated last year
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆28Updated 4 years ago
• mohsaied / rtl2booksim
  Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.
  ☆24Updated 10 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆37Updated 4 years ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆84Updated 6 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• yonseicasl / NeuroSpector
  NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
  ☆21Updated 8 months ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆68Updated 4 months ago
• hngenc / stellar
  ☆32Updated last year
• estwings57 / CasHMC
  CasHMC: A Cycle-accurate Simulator for Hybrid Memory Cube
  ☆23Updated 7 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆49Updated 9 months ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆30Updated 3 weeks ago
• NeuraChip / neurachip
  NeuraChip Accelerator Simulator
  ☆15Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• pku-liang / TensorLib
  A Spatial Accelerator Generation Framework for Tensor Algebra.
  ☆60Updated 4 years ago