Alternatives and similar repositories for SystemC-Components

Users that are interested in SystemC-Components are comparing it to the libraries listed below

• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last month
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆178Updated last week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆159Updated 7 months ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆126Updated 3 years ago
• dcblack / ModernSystemC
  Example code for Modern SystemC using Modern C++
  ☆69Updated 3 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆263Updated 7 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆72Updated 3 years ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆96Updated 6 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆94Updated last month
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated last week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆183Updated last year
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆34Updated 5 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆135Updated last month
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆26Updated 3 years ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 12 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆136Updated last month
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆299Updated this week
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆144Updated last week
• oprecomp / DDR4_controller
  ☆70Updated 4 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆290Updated 2 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆46Updated 4 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆196Updated 3 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆32Updated 6 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆74Updated 6 years ago