Alternatives and similar repositories for SystemC-Components

Users that are interested in SystemC-Components are comparing it to the libraries listed below

• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆60Updated last week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆153Updated 3 months ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆164Updated this week
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆119Updated 2 years ago
• dcblack / ModernSystemC
  Example code for Modern SystemC using Modern C++
  ☆64Updated 2 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆254Updated 3 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆63Updated 2 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆70Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆100Updated 2 months ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆31Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆176Updated 8 months ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆43Updated 3 months ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 11 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆83Updated 10 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated this week
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆92Updated 6 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆77Updated 10 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆188Updated 2 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆44Updated 3 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆51Updated 8 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆67Updated 5 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆54Updated 5 years ago
• quic / qbox
  Qbox
  ☆58Updated last week
• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆97Updated 3 years ago
• hyoukjun / OpenSMART
  Public release
  ☆57Updated 5 years ago