dldldlfma / eyeriss_v1Links
☆12Updated 5 years ago
Alternatives and similar repositories for eyeriss_v1
Users that are interested in eyeriss_v1 are comparing it to the libraries listed below
Sorting:
- ☆113Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- A DNN Accelerator implemented with RTL.☆64Updated 6 months ago
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆197Updated 5 years ago
- IC implementation of Systolic Array for TPU☆260Updated 8 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆105Updated 6 years ago
- ☆41Updated 4 years ago
- IC implementation of TPU☆127Updated 5 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆179Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- ☆44Updated 2 years ago
- Vitis HLS Library for FINN☆202Updated this week
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- ☆65Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆85Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago