nietzhuang / RISC-V-SoC-DesignView external linksLinks
Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.
☆13Oct 31, 2021Updated 4 years ago
Alternatives and similar repositories for RISC-V-SoC-Design
Users that are interested in RISC-V-SoC-Design are comparing it to the libraries listed below
Sorting:
- A scalable Eyeriss model in SystemC.☆33Jan 1, 2023Updated 3 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆13Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 4 months ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- ☆11May 8, 2022Updated 3 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 2 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆15May 16, 2021Updated 4 years ago
- ☆11Mar 10, 2023Updated 2 years ago
- Implemented a two-level (L1 and L2) cache simulator in C++ with round robin eviction policy☆10Jan 4, 2017Updated 9 years ago
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆11Apr 21, 2024Updated last year
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated 11 months ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 7 years ago
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Aug 26, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- ☆11Jul 28, 2022Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- This repository contains the hardware implementation for Static BFP convolution on FPGA☆10Oct 15, 2019Updated 6 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago