pulp-platform / hier-icacheLinks
☆12Updated 4 months ago
Alternatives and similar repositories for hier-icache
Users that are interested in hier-icache are comparing it to the libraries listed below
Sorting:
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- ☆16Updated 6 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- Direct Access Memory for MPSoC☆12Updated last month
- double_fpu_verilog☆15Updated 10 years ago
- OpenCores54x DSP☆9Updated 10 years ago
- Network on Chip for MPSoC☆26Updated last month
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Updated 6 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- NoC based MPSoC☆10Updated 10 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 10 months ago
- WISHBONE Interconnect☆11Updated 7 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- verification of simple axi-based cache☆18Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆14Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 5 months ago
- ☆30Updated 2 months ago
- ☆13Updated 2 years ago
- DSP WishBone Compatible Cores☆14Updated 10 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Verification IP for Watchdog☆11Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆19Updated 10 months ago
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Updated last month
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago
- A configurable general purpose graphics processing unit for☆11Updated 6 years ago