zhehaoxu / ai-talkLinks
关于深度学习算法、框架、编译器、加速器的一些理解
☆16Updated 3 years ago
Alternatives and similar repositories for ai-talk
Users that are interested in ai-talk are comparing it to the libraries listed below
Sorting:
- A scalable Eyeriss model in SystemC.☆28Updated 2 years ago
- ☆44Updated 5 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 4 years ago
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆14Updated 4 years ago
- A small Neural Network Processor for Edge devices.☆11Updated 2 years ago
- ☆12Updated 5 years ago
- ☆33Updated 6 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆65Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆29Updated last year
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- eyeriss-chisel3☆41Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆20Updated 11 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- ☆82Updated last year
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- ☆31Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 4 months ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆129Updated 4 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago
- ☆36Updated 4 years ago