zhehaoxu / ai-talk

Related projects: ⓘ

• dldldlfma / super_small_toy_tpu
  ☆12Updated 3 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆22Updated last year
• zeasa / nvdla-compiler
  ☆41Updated 4 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 5 years ago
• vincent08tw / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆17Updated 3 years ago
• dldldlfma / eyeriss_v1
  ☆10Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆35Updated 2 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆26Updated 4 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆27Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆29Updated last year
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆25Updated 8 months ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆31Updated 4 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆10Updated 4 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆9Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆38Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆12Updated 7 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆22Updated 5 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆9Updated 4 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆19Updated 3 weeks ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆34Updated 4 years ago
• sfox14 / darknet-zynq
  Accelerating DNN inference and training on Zynq
  ☆14Updated 4 years ago
• ym31433 / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆18Updated 7 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆18Updated last year
• jgoeders / dac_sdc_2021
  ☆23Updated 2 years ago
• AILearnerLi / DAC-SDC-2020-SEUer
  ☆26Updated last year
• nqHITSZ / Systolic-Array
  course design
  ☆19Updated 6 years ago
• jgoeders / dac_sdc_2021_designs
  ☆18Updated 2 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆21Updated 3 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆35Updated 3 years ago