zhehaoxu / ai-talkLinks
关于深度学习算法、框架、编译器、加速器的一些理解
☆16Updated 3 years ago
Alternatives and similar repositories for ai-talk
Users that are interested in ai-talk are comparing it to the libraries listed below
Sorting:
- A scalable Eyeriss model in SystemC.☆31Updated 2 years ago
- ☆46Updated 5 years ago
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Updated 2 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- A small Neural Network Processor for Edge devices.☆13Updated 2 years ago
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆15Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆23Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 6 years ago
- ☆35Updated 6 years ago
- ☆22Updated 7 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Eyeriss chip simulator☆38Updated 5 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Updated 6 years ago
- Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).☆16Updated 4 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆39Updated 4 years ago
- A systolic array matrix multiplier☆27Updated 6 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …☆52Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Updated 5 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆41Updated 2 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆34Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆36Updated 4 years ago