Alternatives and similar repositories for ai-talk:

Users that are interested in ai-talk are comparing it to the libraries listed below

• zeasa / nvdla-compiler
  ☆42Updated 5 years ago
• dldldlfma / eyeriss_v1
  ☆12Updated 5 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆36Updated 4 years ago
• dldldlfma / super_small_toy_tpu
  ☆18Updated 4 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆20Updated 3 years ago
• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆25Updated 2 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆30Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆36Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• soDLA-publishment / somnia
  Learn NVDLA by SOMNIA
  ☆32Updated 5 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆27Updated 3 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆30Updated last year
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 2 years ago
• iitm-sysdl / FuSeConv
  Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021
  ☆14Updated 3 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆33Updated 5 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 3 years ago
• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆14Updated 3 years ago
• hsiehong / tpu
  AIChip 2021 project, NCKU
  ☆14Updated 3 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• JunningWu / AIChip
  Aiming at an AI Chip based on RISC-V and NVDLA.
  ☆20Updated 6 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 5 years ago
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆13Updated 5 years ago
• hisrg / Neural-Network-Compression-and-Accelerator-on-Hardware
  My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …
  ☆43Updated 2 years ago
• sfu-arch / SpGEMM
  ☆34Updated 3 years ago
• pulp-platform / stream-ebpc
  Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…
  ☆24Updated 4 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 6 years ago
• SCLUO / ITRI-OpenDLA
  OpenDLA for trying the demo and FPGA solution
  ☆16Updated 2 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆9Updated last year