Alternatives and similar repositories for ai-talk

Users that are interested in ai-talk are comparing it to the libraries listed below

• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆32Updated 3 years ago
• zeasa / nvdla-compiler
  ☆48Updated 6 years ago
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆14Updated 3 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 3 years ago
• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆15Updated 4 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆16Updated 6 years ago
• BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
  This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
  ☆27Updated last year
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆39Updated 5 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆36Updated 2 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆17Updated 7 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆12Updated 2 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆30Updated 6 years ago
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆16Updated 4 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆21Updated 4 years ago
• lllibano / SystolicArray
  A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.
  ☆30Updated 4 months ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆39Updated last year
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 7 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• dldldlfma / eyeriss_v1
  ☆13Updated 6 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆27Updated 5 years ago
• SameLight / ITRI-OpenDLA
  Express DLA implementation for FPGA, revised based on NVDLA.
  ☆11Updated 6 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆39Updated 4 years ago
• WuDan0399 / Integrate-NVDLA-and-TVM
  ☆33Updated 2 years ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆43Updated 2 years ago
• icubecorp / nvdla_compiler
  ☆22Updated 7 years ago
• xliu0709 / WinoCNN
  An HLS based winograd systolic CNN accelerator
  ☆54Updated 4 years ago