Alternatives and similar repositories for ai-talk

Users that are interested in ai-talk are comparing it to the libraries listed below

• nietzhuang / Cycle-accurate-Eyeriss-model
  A scalable Eyeriss model in SystemC.
  ☆31Updated 2 years ago
• zeasa / nvdla-compiler
  ☆46Updated 6 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆35Updated 6 years ago
• hisrg / Neural-Network-Compression-and-Accelerator-on-Hardware
  My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …
  ☆53Updated 2 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆39Updated 5 years ago
• LCAI-TIHU / SW
  LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V
  ☆23Updated 2 years ago
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆13Updated 3 years ago
• yiwangchunyu / AI-RISC
  Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects
  ☆15Updated 4 years ago
• KyleParkJong / Network-on-Chip-Simulator
  Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
  ☆34Updated last year
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆39Updated 4 years ago
• BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
  This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
  ☆25Updated last year
• liang-aquarius / ca_model
  A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…
  ☆16Updated 6 years ago
• openasic-org / xkDLA
  xkDLA：XinKai Deep Learning Accelerator (RTL)
  ☆39Updated last year
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆41Updated 2 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• icubecorp / nvdla_compiler
  ☆22Updated 7 years ago
• nimish15shah / DPU_DAG_Processing_Unit
  RTL code for the DPU chip designed for irregular graphs
  ☆13Updated 3 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• sfu-arch / SpGEMM
  ☆37Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆71Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆19Updated 6 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆60Updated 3 years ago
• jiaaom / HPDLA
  Systolic-array based Deep Learning Accelerator generator
  ☆27Updated 4 years ago
• albertomarchisio / SwiftTron
  ☆46Updated 2 years ago
• WenqiJiang / VGG16_FPGA_Accelerator
  A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…
  ☆34Updated 6 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆24Updated 6 years ago
• zhengchen3 / HLS_Transformer
  c++ version of ViT
  ☆12Updated 3 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆29Updated 6 years ago