☆247Apr 8, 2024Updated 2 years ago
Alternatives and similar repositories for fpga-npu
Users that are interested in fpga-npu are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel implementation of Neural Processing Unit for System on the Chip☆27Jan 19, 2026Updated 2 months ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆171Mar 5, 2025Updated last year
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆303Aug 16, 2018Updated 7 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆13May 17, 2024Updated last year
- An incredibly small 32-bit RISC-V rv32acim CPU capable of running Linux on FPGA, and software simulations.☆31Nov 17, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- ☆43Mar 31, 2025Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 8 years ago
- ☆15Apr 24, 2023Updated 2 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆555Jan 5, 2019Updated 7 years ago
- A scalable Eyeriss model in SystemC.☆34Jan 1, 2023Updated 3 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆197Jan 8, 2026Updated 3 months ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆51Jan 2, 2025Updated last year
- ☆31Aug 8, 2020Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆152Feb 11, 2025Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆173Jun 9, 2023Updated 2 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆252Apr 10, 2023Updated 3 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆119May 11, 2023Updated 2 years ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆880Apr 4, 2026Updated last week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆31Jan 29, 2026Updated 2 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- ☆1,961Updated this week
- ☆29Oct 20, 2019Updated 6 years ago
- ☆26Jun 21, 2024Updated last year
- ☆67May 14, 2022Updated 3 years ago
- A small Neural Network Processor for Edge devices.☆18Nov 22, 2022Updated 3 years ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆95Jan 5, 2025Updated last year
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆12Jan 14, 2026Updated 2 months ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆88Nov 26, 2025Updated 4 months ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 5 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- ☆22Mar 27, 2026Updated 2 weeks ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 5 months ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆29Apr 24, 2025Updated 11 months ago