Matrix Multiplication in Hardware
☆16Jun 3, 2020Updated 6 years ago
Alternatives and similar repositories for Matmul
Users that are interested in Matmul are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆12May 29, 2020Updated 6 years ago
- Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…☆12Jul 4, 2020Updated 5 years ago
- A small Neural Network Processor for Edge devices.☆19Nov 22, 2022Updated 3 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An out-of-order processor that supports multiple instruction sets.☆22Aug 23, 2022Updated 3 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 2 years ago
- Sigma-Delta Analog to Digital Converter in FPGA (VHDL)☆15Dec 19, 2017Updated 8 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆25Jun 28, 2019Updated 6 years ago
- Implementation of CORDIC Algorithms Using Verilog☆26Apr 26, 2021Updated 5 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- OV7670 (Verilog HDL)Drive for FPGA☆19Mar 4, 2019Updated 7 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆30Jan 6, 2026Updated 5 months ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 14 years ago
- A reimplementation of a tiny stack CPU☆89Dec 8, 2023Updated 2 years ago
- ☆39Sep 7, 2025Updated 9 months ago
- The MATLAB code of the local mean decomposition using empirical optimal envelope☆13Jan 6, 2022Updated 4 years ago
- ☆16Aug 21, 2019Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- a 3 voice polyphonic synth on the attiny85☆10Dec 27, 2018Updated 7 years ago
- rv6 is a kernel & operating system written entirely in rust.☆11Nov 7, 2019Updated 6 years ago
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆32Mar 31, 2015Updated 11 years ago
- 😾CET6Cat英语六级辅导网(服务端),Django REST framework。☆10Aug 13, 2019Updated 6 years ago
- ☆36Mar 20, 2025Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆24Jan 13, 2021Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Dec 17, 2025Updated 5 months ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated 3 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- To design test bench of the APB protocol☆21Dec 30, 2020Updated 5 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆130Mar 6, 2026Updated 3 months ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- Applying various image enhancement algorithms on Night Vision IR images using Xilinx Vivado☆16Oct 27, 2023Updated 2 years ago
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year