lycfly / EasyNPULinks
A small Neural Network Processor for Edge devices.
☆12Updated 2 years ago
Alternatives and similar repositories for EasyNPU
Users that are interested in EasyNPU are comparing it to the libraries listed below
Sorting:
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated 2 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆35Updated last year
- A scalable Eyeriss model in SystemC.☆28Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 3 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆21Updated last year
- The official NaplesPU hardware code repository☆18Updated 6 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- ☆47Updated 4 months ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 5 months ago
- ☆15Updated 2 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆14Updated 5 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 5 years ago
- ☆27Updated 5 years ago
- ☆29Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆20Updated last week
- verification of simple axi-based cache☆18Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆25Updated 4 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago