lycfly / EasyNPULinks
A small Neural Network Processor for Edge devices.
☆11Updated 2 years ago
Alternatives and similar repositories for EasyNPU
Users that are interested in EasyNPU are comparing it to the libraries listed below
Sorting:
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆10Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- The official NaplesPU hardware code repository☆17Updated 5 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- DMA controller for CNN accelerator☆13Updated 8 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 4 years ago
- ☆29Updated 4 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆20Updated 11 months ago
- A scalable Eyeriss model in SystemC.☆28Updated 2 years ago
- ☆14Updated 2 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- ☆47Updated 2 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 3 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆15Updated 5 years ago
- Template for project1 TPU☆19Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Tensor Processing Unit implementation in Verilog☆9Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆17Updated last month
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated 2 weeks ago
- ☆27Updated 5 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year