hyoukjun / DesignCNNAccelerators
Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
☆27Updated 6 years ago
Alternatives and similar repositories for DesignCNNAccelerators:
Users that are interested in DesignCNNAccelerators are comparing it to the libraries listed below
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆61Updated 3 years ago
- MAESTRO binary release☆22Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- ☆33Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆33Updated 3 weeks ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆71Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 4 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆45Updated 2 months ago
- ☆34Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated this week
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated 3 weeks ago
- ☆25Updated 10 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆67Updated 5 years ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆20Updated last month
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆36Updated 2 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆22Updated last year
- RTL implementation of Flex-DPE.☆97Updated 4 years ago
- ☆53Updated last year
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆55Updated 3 years ago
- MAERI public release☆31Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆33Updated 2 years ago
- ☆24Updated 5 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- CNN accelerator☆27Updated 7 years ago