Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
☆31Sep 22, 2018Updated 7 years ago
Alternatives and similar repositories for DesignCNNAccelerators
Users that are interested in DesignCNNAccelerators are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Sep 24, 2021Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Feb 16, 2026Updated last month
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆72Dec 29, 2025Updated 2 months ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆36Feb 26, 2026Updated 3 weeks ago
- MAERI public release☆31Sep 8, 2021Updated 4 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆62Dec 3, 2021Updated 4 years ago
- An introductory guide to Bluespec (BSV)☆67May 4, 2019Updated 6 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Apr 14, 2025Updated 11 months ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 7 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- ☆18Oct 3, 2024Updated last year
- ☆12Jul 24, 2018Updated 7 years ago
- MAESTRO binary release☆22Nov 14, 2019Updated 6 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆37Sep 25, 2019Updated 6 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated 2 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆32Mar 7, 2024Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆33Jan 4, 2026Updated 2 months ago
- DS-SLAM implemented on Intel Arria 10 GX 1150☆39Jul 31, 2021Updated 4 years ago
- ☆20Jan 31, 2026Updated last month
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Sep 17, 2025Updated 6 months ago
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆159May 26, 2025Updated 9 months ago
- A scalable Eyeriss model in SystemC.☆34Jan 1, 2023Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Apr 4, 2022Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆45Sep 26, 2023Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆86Aug 28, 2023Updated 2 years ago