hyoukjun / DesignCNNAcceleratorsLinks
Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
☆32Updated 7 years ago
Alternatives and similar repositories for DesignCNNAccelerators
Users that are interested in DesignCNNAccelerators are comparing it to the libraries listed below
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆67Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Updated 11 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆72Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆61Updated 4 years ago
- Public release☆58Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Updated 3 years ago
- ☆29Updated 6 years ago
- ☆45Updated 2 weeks ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 5 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆48Updated last year
- ☆38Updated 3 months ago
- A DSL for Systolic Arrays☆83Updated 7 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- ☆65Updated 9 months ago
- ☆33Updated last year
- HLS for Networks-on-Chip☆39Updated 4 years ago
- ☆35Updated 6 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- eyeriss-chisel3☆40Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- An integrated CGRA design framework☆91Updated 10 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆74Updated 3 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆36Updated 3 years ago