Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
☆31Sep 22, 2018Updated 8 years ago
Alternatives and similar repositories for DesignCNNAccelerators
Users that are interested in DesignCNNAccelerators are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆68Sep 24, 2021Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆41May 1, 2026Updated 4 months ago
- ☆29Oct 20, 2019Updated 6 years ago
- MAERI public release☆33Sep 8, 2021Updated 5 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆78Dec 29, 2025Updated 8 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An introductory guide to Bluespec (BSV)☆69May 4, 2019Updated 7 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆64Dec 3, 2021Updated 4 years ago
- A Bluespec SystemVerilog library of miscellaneous components☆18Jul 10, 2026Updated 2 months ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆22Aug 23, 2018Updated 8 years ago
- A general framework for optimizing DNN dataflow on systolic array☆40Jan 2, 2021Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 3 years ago
- Public release☆60Sep 3, 2019Updated 7 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆15Aug 25, 2023Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆20Oct 3, 2024Updated last year
- ☆13Jul 24, 2018Updated 8 years ago
- MAESTRO binary release☆23Nov 14, 2019Updated 6 years ago
- FPU Generator☆21Updated this week
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆55Mar 24, 2024Updated 2 years ago
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆37Feb 26, 2026Updated 6 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆38Sep 25, 2019Updated 6 years ago
- Cycle Accurate Network-on-Chip Simulator☆38Jul 11, 2026Updated 2 months ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆33Mar 7, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 7 years ago
- ☆21Jan 31, 2026Updated 7 months ago
- Yosys plugin for synthesis of Bluespec code☆17Sep 8, 2021Updated 5 years ago
- A scalable Eyeriss model in SystemC.☆36Jan 1, 2023Updated 3 years ago
- DS-SLAM implemented on Intel Arria 10 GX 1150☆40Jul 31, 2021Updated 5 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 10 years ago
- A fault-injection framework using Chisel and FIRRTL☆39Sep 17, 2025Updated last year
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆173May 26, 2025Updated last year
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆48Apr 4, 2022Updated 4 years ago
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated last month
- A pre-RTL, power-performance model for fixed-function accelerators☆192Jan 17, 2024Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆40Dec 22, 2023Updated 2 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago