Alternatives and similar repositories for Ring-NoC

Users that are interested in Ring-NoC are comparing it to the libraries listed below

• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 11 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 9 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• gjlies / configgpgpu
  A configurable general purpose graphics processing unit for
  ☆11Updated 6 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated last month
• eanchlia / NN_Network_On_Chip
  Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…
  ☆12Updated 6 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
  EE577b-Course-Project
  ☆18Updated 5 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 3 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆14Updated 9 years ago
• pulp-platform / hier-icache
  ☆12Updated 4 months ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆23Updated last year
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 3 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆12Updated 5 years ago
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated last year
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆19Updated 7 years ago
• freecores / an-fpga-implementation-of-low-latency-noc-based-mpsoc
  NoC based MPSoC
  ☆11Updated 11 years ago
• pulp-platform / cluster_interconnect
  ☆13Updated last month
• pulp-platform / jtag_pulp
  ☆13Updated 2 years ago
• hossamfadeel / Verilog-Based-NoC-Simulator
  Verilog-Based-NoC-Simulator
  ☆10Updated 9 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• vinodsake / Last-Level-Cache-Simulator
  ☆12Updated 8 years ago
• pulp-platform / ace
  ☆16Updated 2 weeks ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year