brilacasck / micro-acc-systemc
simulating connection of micro processor and accelerator on a bus context with systemc language
☆13Updated 6 years ago
Alternatives and similar repositories for micro-acc-systemc:
Users that are interested in micro-acc-systemc are comparing it to the libraries listed below
- RISC-V Embedded Processor for Approximate Computing☆125Updated last week
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆18Updated 2 years ago
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆13Updated 6 years ago
- CMake based hardware build system☆16Updated last week
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- A repository for SystemC Learning examples☆67Updated 2 years ago
- ☆25Updated this week
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆12Updated last month
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- Hardware Description Language Translator☆16Updated this week
- SystemC training aimed at TLM.☆28Updated 4 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆19Updated 4 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 4 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Updated last year
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- Simple implementation of I2C interface written on Verilog and SystemC☆42Updated 7 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆27Updated 7 months ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- Connecting SystemC with SystemVerilog☆40Updated 13 years ago
- My local copy of UVM-SystemC☆12Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆98Updated 4 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆41Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- TUM EI7402 SystemC laboratory assignments☆9Updated 3 years ago
- Import and export IP-XACT XML register models☆34Updated 6 months ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago