brilacasck / micro-acc-systemc
simulating connection of micro processor and accelerator on a bus context with systemc language
☆13Updated 6 years ago
Alternatives and similar repositories for micro-acc-systemc
Users that are interested in micro-acc-systemc are comparing it to the libraries listed below
Sorting:
- A repository for SystemC Learning examples☆68Updated 2 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Development of a Network on Chip Simulation using SystemC.☆32Updated 7 years ago
- SystemC training aimed at TLM.☆29Updated 4 years ago
- RISC V core implementation using Verilog.☆26Updated 4 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆63Updated 11 months ago
- ☆25Updated last week
- Implementation of a cache memory in verilog☆14Updated 7 years ago
- Archives of SystemC from The Ground Up Book Exercises☆30Updated 2 years ago
- Simple runtime for Pulp platforms☆47Updated this week
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated last week
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆19Updated 5 months ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- SystemC to Verilog Synthesizable Subset Translator☆10Updated 2 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Platform Level Interrupt Controller☆40Updated last year
- An open-source 32-bit RISC-V soft-core processor☆34Updated 3 weeks ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- ☆26Updated 4 years ago
- Simple RiscV core for academic purpose.☆22Updated 5 years ago
- VGA LCD Core (OpenCores)☆14Updated 6 years ago
- Network on Chip for MPSoC☆26Updated last week
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆54Updated 9 months ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 6 months ago
- Another tiny RISC-V implementation☆55Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago