EPFL logic synthesis benchmarks
☆228Nov 18, 2025Updated 3 months ago
Alternatives and similar repositories for benchmarks
Users that are interested in benchmarks are comparing it to the libraries listed below
Sorting:
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,124Updated this week
- Showcase examples for EPFL logic synthesis libraries☆202Apr 5, 2024Updated last year
- C++ logic network library☆278Sep 30, 2025Updated 5 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆117May 18, 2023Updated 2 years ago
- Optimization results for superconducting electronic (SCE) circuits☆18Dec 5, 2023Updated 2 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆84Dec 5, 2025Updated 2 months ago
- IDEA project source files☆111Oct 15, 2025Updated 4 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆26May 29, 2022Updated 3 years ago
- ☆13Dec 31, 2022Updated 3 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆64Jan 13, 2025Updated last year
- GPU-based logic synthesis tool☆97Nov 27, 2025Updated 3 months ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆29Oct 17, 2020Updated 5 years ago
- AIGER And-Inverter-Graph Library☆97Feb 17, 2026Updated last week
- Research paper based on or related to ABC.☆70Jan 19, 2026Updated last month
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆25Apr 9, 2025Updated 10 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- A logic synthesis tool☆84Sep 8, 2025Updated 5 months ago
- Simple Python interface for ABC☆29May 19, 2023Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- A circuit toolkit☆107Feb 23, 2020Updated 6 years ago
- ☆15May 24, 2023Updated 2 years ago
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 2 years ago
- An advanced circuit-based sat solver☆36Feb 24, 2025Updated last year
- C++ header-only exact synthesis library☆17Jan 18, 2023Updated 3 years ago
- C++ header-only reasoning library☆16Jul 11, 2024Updated last year
- Problems and Results of IWLS 2023 Programming Contest☆16Apr 12, 2025Updated 10 months ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Nov 13, 2023Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆25Jul 12, 2023Updated 2 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 5 years ago
- Python version of tools to work with AIG formatted files☆12May 20, 2025Updated 9 months ago
- Problems and Results of IWLS 2022 Programming Contest☆21Apr 12, 2025Updated 10 months ago
- ☆19Dec 21, 2020Updated 5 years ago
- GNN-RE datasets for circuit recognition☆56May 16, 2023Updated 2 years ago