Alternatives and similar repositories for benchmarks

Users that are interested in benchmarks are comparing it to the libraries listed below

• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆59Updated last week
• lsils / mockturtle
  C++ logic network library
  ☆262Updated last month
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆69Updated last week
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 10 months ago
• nbulsi / also
  A logic synthesis tool
  ☆82Updated 2 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆35Updated 4 months ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆136Updated 3 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆160Updated 6 months ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆200Updated last year
• zshi0616 / python-deepgate
  ☆25Updated last year
• lnis-uofu / LSOracle
  IDEA project source files
  ☆109Updated last month
• zshi0616 / DeepGate2
  ☆31Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆93Updated this week
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆107Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆132Updated last year
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆186Updated 6 months ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆65Updated 6 months ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆97Updated 4 months ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆138Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• The-OpenROAD-Project / RePlAce
  RePlAce global placement tool
  ☆241Updated 5 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆82Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆44Updated last year
• krzhu / abc_py
  Simple Python interface for ABC
  ☆25Updated 2 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆20Updated 10 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆18Updated 7 months ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 5 years ago
• pkuzjx / EDA-wiki
  EDA wiki
  ☆133Updated 2 weeks ago
• The-OpenROAD-Project / asap7
  ☆208Updated 8 months ago