lsils / benchmarks
EPFL logic synthesis benchmarks
☆183Updated 7 months ago
Alternatives and similar repositories for benchmarks:
Users that are interested in benchmarks are comparing it to the libraries listed below
- A logic synthesis tool☆73Updated last week
- IDEA project source files☆106Updated 5 months ago
- C++ logic network library☆226Updated 5 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆45Updated 3 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆26Updated this week
- Showcase examples for EPFL logic synthesis libraries☆194Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆124Updated 6 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆137Updated last month
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆157Updated 3 months ago
- Research paper based on or related to ABC.☆33Updated last week
- Rsyn – An Extensible Physical Synthesis Framework☆125Updated 8 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆170Updated 5 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆54Updated 2 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆25Updated 5 years ago
- GPU-based logic synthesis tool☆81Updated 9 months ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆119Updated 4 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆101Updated last year
- ☆22Updated 9 months ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆86Updated last year
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆112Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆130Updated 2 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 3 months ago
- ☆151Updated last month
- Problems and Results of IWLS 2022 Programming Contest☆18Updated this week
- ☆103Updated 5 years ago
- EDA physical synthesis optimization kit☆51Updated last year
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 4 years ago
- ☆138Updated 3 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆133Updated 2 years ago