Alternatives and similar repositories for DRiLLS

Users that are interested in DRiLLS are comparing it to the libraries listed below

• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆141Updated 5 months ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆29Updated 5 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated 2 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• cuhk-eda / dr-cu
  Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
  ☆141Updated 2 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆32Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆142Updated 2 years ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆167Updated 8 months ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆86Updated last year
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆224Updated 2 months ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆53Updated last year
• NVlabs / CircuitOps
  ☆97Updated 6 months ago
• krzhu / abc_py
  Simple Python interface for ABC
  ☆26Updated 2 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆30Updated 3 years ago
• IntelLabs / FloorSet
  ☆78Updated 2 weeks ago
• thu-nics / awesome_ai4eda
  ☆278Updated 5 years ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆11Updated 9 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated 7 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆79Updated 7 years ago
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆16Updated 2 years ago
• cuhk-eda / REST
  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
  ☆59Updated 3 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆75Updated last month
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆26Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆150Updated 7 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆61Updated last year