lsils / bill

Related projects: ⓘ

• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆22Updated last year
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated last year
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆35Updated 2 months ago
• msoeken / kitty
  C++ truth table library
  ☆49Updated 5 months ago
• gmeuli / caterpillar
  ☆22Updated 3 years ago
• msoeken / cirkit
  A circuit toolkit
  ☆95Updated 4 years ago
• cda-tum / fiction
  An open-source design automation framework for Field-coupled Nanotechnologies
  ☆56Updated this week
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆176Updated 5 months ago
• fmozafari / angel
  C++ Library for Quantum State Preparation (QSP)
  ☆10Updated last year
• lsils / mockturtle
  C++ logic network library
  ☆204Updated this week
• msoeken / revkit
  RevKit: Python quantum compilation library and framework
  ☆24Updated 5 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆61Updated 3 years ago
• nbulsi / also
  A logic synthesis tool
  ☆64Updated last year
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆57Updated 3 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆16Updated 2 years ago
• msoeken / alice
  C++ command shell library
  ☆51Updated 3 years ago
• boschmitt / tweedledum
  C++17 Library for analysis, compilation/synthesis, and optimization of quantum circuits
  ☆97Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆29Updated 3 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆93Updated 2 weeks ago
• amahzoon / genmul
  ☆14Updated 3 years ago
• msoeken / reversible-sota
  State-of-the-art in reversible logic synthesis
  ☆12Updated 8 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆17Updated 3 weeks ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆13Updated 7 years ago
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆21Updated last year
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆20Updated last year
• ckchengucsd / ILP-SAT-Detailed-Router
  ILP SAT Detailed Router
  ☆11Updated 4 years ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆159Updated 3 weeks ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated 4 months ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago