MLCAD 2020: Reinforcement for logic optimization sequence exploration
☆29Oct 17, 2020Updated 5 years ago
Alternatives and similar repositories for abcRL
Users that are interested in abcRL are comparing it to the libraries listed below
Sorting:
- Simple Python interface for ABC☆29May 19, 2023Updated 2 years ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆117May 18, 2023Updated 2 years ago
- ☆13Dec 31, 2022Updated 3 years ago
- discrete gate sizing☆14Nov 23, 2020Updated 5 years ago
- Awesome machine learning for logic synthesis☆30Sep 21, 2022Updated 3 years ago
- EPFL logic synthesis benchmarks☆231Nov 18, 2025Updated 3 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- ☆18May 23, 2021Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆67Jan 13, 2025Updated last year
- ☆21Nov 18, 2022Updated 3 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Dec 23, 2024Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆26Apr 9, 2025Updated 10 months ago
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Jan 23, 2020Updated 6 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆26May 29, 2022Updated 3 years ago
- ☆14Oct 8, 2024Updated last year
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Nov 13, 2023Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- ☆15May 24, 2023Updated 2 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Jul 15, 2021Updated 4 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- Collection of digital hardware modules & projects (benchmarks)☆84Dec 5, 2025Updated 2 months ago
- just checking☆21Jun 29, 2022Updated 3 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆41Dec 24, 2025Updated 2 months ago
- Cross platform Instant Outbidding Bot, Instant Outbidder Bot is designed to outbid all real-time bids within a second by percentage incre…☆100Jan 17, 2023Updated 3 years ago
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 3 years ago
- ☆16May 11, 2018Updated 7 years ago
- A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COrouti…☆21Dec 24, 2023Updated 2 years ago
- ☆18Mar 29, 2022Updated 3 years ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 2 months ago
- Benchmarks for Approximate Circuit Synthesis☆17Aug 2, 2020Updated 5 years ago
- Implementation of CoDAIL in the ICLR 2020 paper <Multi-Agent Interactions Modeling with Correlated Policies>☆19Jun 17, 2021Updated 4 years ago
- SMT-based-STDCELL-Layout-Generator☆18Sep 30, 2021Updated 4 years ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆16Apr 7, 2023Updated 2 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,124Feb 26, 2026Updated last week
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago