Alternatives and similar repositories for GNN-RE

Users that are interested in GNN-RE are comparing it to the libraries listed below

• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.
  ☆70Updated 4 months ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆25Updated 3 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆54Updated 10 months ago
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆27Updated last year
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆136Updated 3 months ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆44Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆69Updated last week
• zshi0616 / DeepGate2
  ☆31Updated last year
• IntelLabs / FloorSet
  ☆77Updated 5 months ago
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆51Updated last year
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆65Updated 6 months ago
• lnis-uofu / ML-Mapper
  ☆13Updated 2 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆82Updated last year
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• DfX-NYUAD / GNNUnlock
  ☆16Updated 3 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 7 months ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆29Updated 3 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆58Updated 5 months ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 5 years ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆27Updated 7 months ago
• CODA-Team / AncstrGNN_benchmark
  Analog IC symmetry extraction benchmark of AncstrGNN
  ☆10Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 10 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆55Updated 5 months ago
• PKU-IDEA / SymDetect
  Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks
  ☆15Updated 2 years ago