Alternatives and similar repositories for lstools-showcase

Users that are interested in lstools-showcase are comparing it to the libraries listed below

• lsils / mockturtle
  C++ logic network library
  ☆272Updated 3 months ago
• nbulsi / also
  A logic synthesis tool
  ☆84Updated 3 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 2 months ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆224Updated last month
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆60Updated 11 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆64Updated last month
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆135Updated last year
• msoeken / cirkit
  A circuit toolkit
  ☆106Updated 5 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆39Updated last week
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆38Updated last year
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆189Updated 7 months ago
• pkuzjx / eda-collection
  ☆107Updated 6 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated 3 weeks ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆121Updated 4 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 3 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆108Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆94Updated 4 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆230Updated this week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆133Updated 6 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆36Updated 5 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆32Updated 3 years ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆85Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆141Updated 2 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆94Updated 4 months ago