Alternatives and similar repositories for lstools-showcase

Users that are interested in lstools-showcase are comparing it to the libraries listed below

• lsils / mockturtle
  C++ logic network library
  ☆231Updated last week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆106Updated 6 months ago
• nbulsi / also
  A logic synthesis tool
  ☆73Updated last month
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆191Updated 8 months ago
• msoeken / cirkit
  A circuit toolkit
  ☆101Updated 5 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆157Updated 4 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆125Updated 9 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆47Updated 4 months ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆36Updated 10 months ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆223Updated this week
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆40Updated last week
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated 2 weeks ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆91Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆58Updated last week
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆54Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆104Updated last year
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆58Updated 11 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆131Updated 5 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆17Updated 2 years ago
• parallaxsw / OpenSTA
  ☆67Updated this week
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆76Updated last month
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆135Updated 2 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆113Updated 4 years ago
• sunmagnetics / RSFQlib
  RSFQ cell library
  ☆38Updated 2 years ago
• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆460Updated 2 weeks ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆87Updated 4 years ago
• ncsu-eda / FreePDK3
  ☆144Updated 3 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆26Updated 2 years ago