msoeken / cirkit

Related projects ⓘ

Alternatives and complementary repositories for cirkit

• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆184Updated 7 months ago
• lsils / mockturtle
  C++ logic network library
  ☆212Updated last month
• msoeken / kitty
  C++ truth table library
  ☆51Updated 7 months ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆23Updated 2 years ago
• lsils / bill
  C++ header-only reasoning library
  ☆11Updated 4 months ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆35Updated 4 months ago
• gmeuli / caterpillar
  ☆22Updated 4 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated last year
• nbulsi / also
  A logic synthesis tool
  ☆68Updated 2 years ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆166Updated 2 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆61Updated 4 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆61Updated 5 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆98Updated 2 weeks ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆206Updated this week
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆55Updated 5 months ago
• msoeken / revkit
  RevKit: Python quantum compilation library and framework
  ☆24Updated 5 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆47Updated last week
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆53Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• rdaly525 / coreir
  ☆101Updated 2 years ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆11Updated 11 months ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆102Updated 3 years ago
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆54Updated 2 years ago
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆23Updated last year
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆20Updated this week
• ben-marshall / verilog-parser
  A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
  ☆128Updated 5 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆23Updated 4 years ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆19Updated 2 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆29Updated 3 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆25Updated 4 months ago