Alternatives and similar repositories for cirkit

Users that are interested in cirkit are comparing it to the libraries listed below

• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆195Updated last year
• lsils / mockturtle
  C++ logic network library
  ☆246Updated 2 weeks ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆37Updated last year
• lsils / kitty
  C++ truth table library
  ☆59Updated 3 weeks ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆86Updated 3 weeks ago
• gmeuli / caterpillar
  ☆26Updated 4 years ago
• lsils / bill
  C++ header-only reasoning library
  ☆17Updated last year
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• nbulsi / also
  A logic synthesis tool
  ☆78Updated last month
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆227Updated last week
• classabbyamp / espresso-logic
  A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
  ☆154Updated 5 years ago
• SPbSAT / cirbo
  ☆22Updated 2 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated last week
• msoeken / revkit
  RevKit: Python quantum compilation library and framework
  ☆30Updated 6 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆21Updated 4 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆51Updated last month
• msoeken / reversible-sota
  State-of-the-art in reversible logic synthesis
  ☆22Updated 9 years ago
• amahzoon / genmul
  ☆17Updated 4 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated last week
• aziesemer / astran
  ASTRAN - Automatic Synthesis of Transistor Networks
  ☆64Updated 3 years ago
• marcelwa / aigverse
  A Python library for working with logic networks, synthesis, and optimization.
  ☆65Updated this week
• cuddorg / cudd
  CUDD Decision Diagram Package
  ☆142Updated 3 weeks ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆208Updated last month
• rdaly525 / coreir
  ☆103Updated 3 years ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆16Updated 8 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆35Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago