Alternatives and similar repositories for phySAT:

Users that are interested in phySAT are comparing it to the libraries listed below

• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆25Updated 2 years ago
• Entropy-xcy / sns
  ☆14Updated 2 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆21Updated last week
• lnis-uofu / ML-Mapper
  ☆9Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆78Updated 6 months ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆16Updated 3 months ago
• amahzoon / genmul
  ☆14Updated 4 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆22Updated 8 months ago
• zshi0616 / python-deepgate
  ☆21Updated 6 months ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated 2 years ago
• ABKGroup / TritonRoute-WXL
  ☆26Updated 4 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• nbulsi / also
  A logic synthesis tool
  ☆72Updated 2 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆18Updated 3 weeks ago
• cure-lab / DeepGate2
  ☆14Updated last year
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆12Updated 3 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆39Updated 4 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆24Updated this week
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆36Updated 2 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆26Updated 6 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆39Updated this week
• Daikon-Sun / Routing-Visualization
  Routing Visualization for Physical Design
  ☆18Updated 6 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆24Updated 5 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆49Updated 4 years ago
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 5 years ago
• ABKGroup / RosettaStone
  ☆22Updated 2 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator
  SMT-based-STDCELL-Layout-Generator
  ☆16Updated 3 years ago
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆10Updated 8 years ago